# Multiplexer

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This article is about electronic switching. For telecommunications, see multiplexing.
Schematic of a 2-to-1 Multiplexer. It can be equated to a controlled switch.
Schematic of a 1-to-2 Demultiplexer. Like a multiplexer, it can be equated to a controlled switch.

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line.[1] A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output.[2] Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.[1] A multiplexer is also called a data selector.

An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal.

Conversely, a demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. A multiplexer is often used with a complementary demultiplexer on the receiving end.[1]

An electronic multiplexer can be considered as a multiple-input, single-output switch, and a demultiplexer as a single-input, multiple-output switch.[3] The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and the short parallel side containing the output pin.[4] The schematic on the right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right. The $sel$ wire connects the desired input to the output.

## Cost saving

The basic function of a multiplexer: combining multiple inputs into a single data stream. On the receiving side, a demultiplexer splits the single data stream into the original multiple signals.

One use for multiplexers is cost saving by connecting a multiplexer and a demultiplexer (or demux) together over a single channel (by connecting the multiplexer's single output to the demultiplexer's single input). The image to the right demonstrates this. In this case, the cost of implementing separate channels for each data source is higher than the cost and inconvenience of providing the multiplexing/demultiplexing functions.

At the receiving end of the data link a complementary demultiplexer is normally required to break single data stream back down into the original streams. In some cases, the far end system may have more functionality than a simple demultiplexer and so, while the demultiplexing still exists logically, it may never actually happen physically. This would be typical where a multiplexer serves a number of IP network users and then feeds directly into a router which immediately reads the content of the entire link into its routing processor and then does the demultiplexing in memory from where it will be converted directly into IP sections.

Often, a multiplexer and demultiplexer are combined together into a single piece of equipment, which is usually referred to simply as a "multiplexer". Both pieces of equipment are needed at both ends of a transmission link because most communications systems transmit in both directions.

In analog circuit design, a multiplexer is a special type of analog switch that connects one signal selected from several inputs to a single output.

## Digital multiplexers

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect $\scriptstyle I_0$ to the output while a logic value of 1 would connect $\scriptstyle I_1$ to the output. In larger multiplexers, the number of selector pins is equal to $\scriptstyle \left \lceil \log_2(n) \right \rceil$ where $\scriptstyle n$ is the number of inputs.

For example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs would require no fewer than 5 selector pins. The binary value expressed on these selector pins determines the selected input pin.

A 2-to-1 multiplexer has a boolean equation where $\scriptstyle A$ and $\scriptstyle B$ are the two inputs, $\scriptstyle S$ is the selector input, and $\scriptstyle Z$ is the output:

$Z = ( A \cdot \overline{S}) + (B \cdot S)$
A 2-to-1 mux

Which can be expressed as a truth table:

 $\scriptstyle S$ $\scriptstyle A$ $\scriptstyle B$ $\scriptstyle Z$ 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0

This truth table shows that when $\scriptstyle S=0$ then $\scriptstyle Z=A$ but when $\scriptstyle S=1$ then $\scriptstyle Z=B$. A straightforward realization of this 2-to-1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate.

Larger multiplexers are also common and, as stated above, require $\scriptstyle \left \lceil \log_2(n) \right \rceil$ selector pins for $n$ inputs. Other common sizes are 4-to-1, 8-to-1, and 16-to-1. Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control a number of inputs for the given number of selector inputs.

The boolean equation for a 4-to-1 multiplexer is:

$F = (A \cdot \overline{S_0} \cdot \overline{S_1}) + (B \cdot \overline{S_0} \cdot S_1) + (C \cdot S_0 \cdot \overline{S_1} ) + (D \cdot S_0 \cdot S_1)$

The following 4-to-1 multiplexer is constructed from 3-state buffers and AND gates (the AND gates are acting as the decoder):

Note that the subscripts on the $\scriptstyle I_n$ inputs indicate the decimal value of the binary control inputs at which that input is let through.

### Chaining multiplexers

Larger multiplexers can be constructed by using smaller multiplexers by chaining them together. For example, an 8-to-1 multiplexer can be made with two 4-to-1 and one 2-to-1 multiplexers. The two 4-to-1 multiplexer outputs are fed into the 2-to-1 with the selector pins on the 4-to-1's put in parallel giving a total number of selector inputs to 3, which is equivalent to an 8-to-1.

### List of ICs which provide multiplexing

The 7400 series has several ICs that contain multiplexer(s):

S.No. IC No. Function Output State
1 74157 Quad 2:1 mux. Output same as input given
2 74158 Quad 2:1 mux. Output is inverted input
0 74153 Dual 4:1 mux. Output same as input
5 74352 Dual 4:1 mux. Output is inverted input
9 74151A 16:1 mux. Both outputs available (i.e., complementary outputs)
6 74151 8:1 mux. Output is inverted input
7 74150 16:1 mux. Output is inverted input

## Digital demultiplexers

Demultiplexers take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs depending on the values of the selection inputs. Demultiplexers are sometimes convenient for designing general purpose logic, because if the demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any function of the selection bits can be constructed by logically OR-ing the correct set of outputs.

If X is the input and S is the selector, and A and B are the outputs:

$A = ( X \cdot \overline{S})$

$B = ( X \cdot S)$

Example: A Single Bit 1-to-4 Line Demultiplexer

### List of ICs which provide demultiplexing

The 7400 series has several ICs that contain demultiplexer(s):

S.No. IC No. (7400) IC No. (4000) Function Output State
1 74139 Dual 1:4 demux. Output is inverted input
3 74156 Dual 1:4 demux. Output is open collector
4 74138 1:8 demux. Output is inverted input
5 74238 1:8 demux.
6 74154 1:16 demux. Output is inverted input
7 74159 CD4514/15 1:16 demux. Output is open collector and same as input

## Multiplexers as PLDs

Multiplexers can also be used as components of programmable logic devices. By specifying the logic arrangement in the input signals, a custom logic circuit can be created. The selector inputs then act as the logic inputs. This is especially useful in situations when cost is a factor and for modularity.

## References

1. ^ a b c Dean, Tamara (2010). Network+ Guide to Networks. Delmar. pp. 82–85.
2. ^ Debashis, De (2010). Basic Electronics. Dorling Kindersley. p. 557.
3. ^ Lipták, Béla (2002). Instrument engineers' handbook: Process software and digital networks. CRC Press. p. 343.
4. ^ Harris, David (2007). Digital Design and Computer Architecture. Penrose. p. 79.