Zero instruction set computer
||This article appears to be written like an advertisement. (May 2012)|
Zero instruction set computers should not be confused with analogue computers. Analogue computers do not have the ability to carry out instructions.
The ZISC architecture alleviates the memory bottleneck by blending the pattern memory with the pattern learning and recognition logic.
The main innovation was finding a way to solve the "winner takes all problem" and allows a constant learning/recognition time, regardless of the number of processing elements (e.g. neurons) connected in parallel.
The first ZISC35 with 36 neurons was released in 1993 and the ZISC78 in 2000 both by IBM which discontinued the manufacturing in 2001.
In August 2007, the CM1K (CogniMem 1,024 neurons) was introduced by CogniMem Ltd. CM1K was designed by Anne Menendez and Guy Paillet.
- "CogniMem Technologies Inc. Technology Background". Retrieved 2012-03-08.
- US Patent for ZISC hardware, issued to IBM/G.Paillet on April 15, 1997
- Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems by K. Madani, G. de Trémiolles, and P. Tannhof
- From CISC to RISC to ZISC by S. Liebman on lsmarketing.com
- Neural Networks on Silicon at aboutAI.net
- Zero instruction set computer at DMOZ
- NeuroMem CM1K chip, successor of the ZISC, designed by G.Paillet/General Vision
- CogniMem Technologies Inc. Massively Parallel Hardware Acceleration for Pattern Recognition