Zero instruction set computer
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In computer science, Zero Instruction Set Computer (ZISC) refers to a computer architecture based on pure pattern matching and absence of (micro-)instructions in the classical sense. The ZISC acronym alludes to the previously developed RISC (Reduced Instruction Set Computer) technology.
The ZISC architecture alleviates the memory bottleneck by blending the pattern memory with the pattern learning and recognition logic. The main innovation was finding a way to solve the "winner takes all problem" and allows a constant learning/recognition time, regardless of the number of processing elements (e.g. neurons) connected in parallel.
The first ZISC35 with 36 neurons was released in 1993 and the ZISC78 in 2000 both by IBM which discontinued the manufacturing in 2001.
In August 2007,the CM1K (CogniMem 1,024 neurons) was introduced by CogniMem Ltd. CM1K was designed by Anne Menendez and Guy Paillet.
- "CogniMem Technologies Inc. Technology Background". Retrieved 2012-03-08.
See also 
- US Patent for ZISC hardware, issued to IBM/G.Paillet on April 15, 1997
- Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems by K. Madani, G. de Trémiolles, and P. Tannhof
- From CISC to RISC to ZISC by S. Liebman on lsmarketing.com
- Neural Networks on Silicon at aboutAI.net
- Zero instruction set computer at the Open Directory Project
- CogniMem Technologies Inc. Massively Parallel Hardware Acceleration for Pattern Recognition