I486SX: Difference between revisions
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In fact, at least one person claiming to be an Intel test engineer responsible for 486DX and 486SX testing during that period states that all of the above speculation is incorrect. Even the first 486SX units were similar but distinct chips from the 486DX. These units were committed to be 486SX units at the time the wafers were started in the fab, not after testing. The CPUID, a code meant to identify the type of chip, was hardwired on the chips during production so that they could not be switched after testing (or after sale). The floating point unit was not disconnected by laser but disabled using a bond wire option. A bond wire in the package tied a disable floating point (DFP) input pad to power or ground to control whether the FPU was enabled or disabled. 486SX units were tested to specification with the FPU disabled. The FPU functionality was not tested in production, and most of the FPUs would work correctly on 486SX units if they were enabled. If the FPU had a defect which would impact 486SX functionality even when the FPU was disabled, the units would fail production testing. The motivation for the 486SX was [[price discrimination]]. By segmenting the 486 family into these two classes of products, Intel could offer the less expensive 486SX for customers who were more price sensitive without comprising the price for the 486DX paid by less price sensitive customers. Price discrimination is a common strategy for hardware and software products. |
In fact, at least one person claiming to be an Intel test engineer responsible for 486DX and 486SX testing during that period states that all of the above speculation is incorrect. Even the first 486SX units were similar but distinct chips from the 486DX. These units were committed to be 486SX units at the time the wafers were started in the fab, not after testing. The CPUID, a code meant to identify the type of chip, was hardwired on the chips during production so that they could not be switched after testing (or after sale). The floating point unit was not disconnected by laser but disabled using a bond wire option. A bond wire in the package tied a disable floating point (DFP) input pad to power or ground to control whether the FPU was enabled or disabled. 486SX units were tested to specification with the FPU disabled. The FPU functionality was not tested in production, and most of the FPUs would work correctly on 486SX units if they were enabled. If the FPU had a defect which would impact 486SX functionality even when the FPU was disabled, the units would fail production testing. The motivation for the 486SX was [[price discrimination]]. By segmenting the 486 family into these two classes of products, Intel could offer the less expensive 486SX for customers who were more price sensitive without comprising the price for the 486DX paid by less price sensitive customers. Price discrimination is a common strategy for hardware and software products. |
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Intel did not publish internal implementation details so this won't be found in an Intel publication, just like there is no reliable source for the broadly disseminated speculation in the first paragraph. The scenario described in the second paragraph has the advantage of being the truth. In a situation where there is no |
Intel did not publish internal implementation details so this won't be found in an Intel publication, just like there is no reliable source for the broadly disseminated speculation in the first paragraph. The scenario described in the second paragraph has the advantage of being the truth. In a situation where there is no official citation for either scenario, people should be aware of both. |
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There were at least three versions of the 486SX, all of which had distinct CPUIDs as compared to 486DX devices. The first version was on a 1.0 micron process and sold in a PGA package. The second version was on the next generation 0.8 micron process, which used less power. Less heat generation allowed it to be included in a less expensive PQFP package. The PQFP package allowed the 486SX to be surface-mounted on PC boards. The third version had the FPU unit completely removed. This reduced die size and thus improved yields and reduced costs. |
There were at least three versions of the 486SX, all of which had distinct CPUIDs as compared to 486DX devices. The first version was on a 1.0 micron process and sold in a PGA package. The second version was on the next generation 0.8 micron process, which used less power. Less heat generation allowed it to be included in a less expensive PQFP package. The PQFP package allowed the 486SX to be surface-mounted on PC boards. The third version had the FPU unit completely removed. This reduced die size and thus improved yields and reduced costs. |
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Revision as of 21:18, 28 December 2009
Many people believe that the Intel's i486SX was a modified Intel 486DX microprocessor with its floating-point unit (FPU) disconnected. They speculate that all early 486SX chips were actually i486DX chips with a defective FPU. Their theory is that Intel yields were poor and that the motivation for the 486SX was to salvage 486DX units with a defective FPU. If testing showed that the central processing unit was working but the FPU was defective, the FPU's power and bus connections were destroyed with a laser and the chip was sold cheaper as an SX; if the FPU worked it was sold as a DX. Although people repeat this speculation in many places on the web, there is no reliable citation to an Intel source or any evidence that supports it. Its gossip that has been accepted as true because of sheer repetition and silence by Intel on the matter.
In fact, at least one person claiming to be an Intel test engineer responsible for 486DX and 486SX testing during that period states that all of the above speculation is incorrect. Even the first 486SX units were similar but distinct chips from the 486DX. These units were committed to be 486SX units at the time the wafers were started in the fab, not after testing. The CPUID, a code meant to identify the type of chip, was hardwired on the chips during production so that they could not be switched after testing (or after sale). The floating point unit was not disconnected by laser but disabled using a bond wire option. A bond wire in the package tied a disable floating point (DFP) input pad to power or ground to control whether the FPU was enabled or disabled. 486SX units were tested to specification with the FPU disabled. The FPU functionality was not tested in production, and most of the FPUs would work correctly on 486SX units if they were enabled. If the FPU had a defect which would impact 486SX functionality even when the FPU was disabled, the units would fail production testing. The motivation for the 486SX was price discrimination. By segmenting the 486 family into these two classes of products, Intel could offer the less expensive 486SX for customers who were more price sensitive without comprising the price for the 486DX paid by less price sensitive customers. Price discrimination is a common strategy for hardware and software products.
Intel did not publish internal implementation details so this won't be found in an Intel publication, just like there is no reliable source for the broadly disseminated speculation in the first paragraph. The scenario described in the second paragraph has the advantage of being the truth. In a situation where there is no official citation for either scenario, people should be aware of both.
There were at least three versions of the 486SX, all of which had distinct CPUIDs as compared to 486DX devices. The first version was on a 1.0 micron process and sold in a PGA package. The second version was on the next generation 0.8 micron process, which used less power. Less heat generation allowed it to be included in a less expensive PQFP package. The PQFP package allowed the 486SX to be surface-mounted on PC boards. The third version had the FPU unit completely removed. This reduced die size and thus improved yields and reduced costs.
Computer Manufacturers that used these processors include Packard Bell, Compaq and IBM. Back in the early 1990s it wasn't advantageous for most users to have a FPU. On one hand, many typical applications like word processing and email do not use floating point operations. On the other hand, those involved in heavy computer gaming or mathematical work generally benefit from a FPU.
Some systems allowed the user to upgrade the i486SX to a CPU with a FPU. The FPU upgrade device was shipped as the i487, which had the same functionality as the i486DX chip, but with a distinct CPUID and an extra pin. The i487 was installed in an upgrade socket and the extra pin was either a power or ground pin that indicated that the i487 was installed. That signal from the extra pin was used to disable the i486SX when the i487 was installed. Although i486SX devices were not used at all when the i487 was installed, they were hard to remove because the i486SX was installed in non-ZIF sockets or in a plastic package that was surface mounted on the motherboard.
References
This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.