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|L1 cache||Pentium Pro: 16 KB per core(8 KB I cache + 8 KB D cache) Pentium II/3: 32 KB(16 KB I cache + 16 KB D cache)|
|L2 cache||128 KB to 512 KB|
256 KB to 2048 KB (Xeon)
|Created||November 1, 1995|
|Transistors||7.5M 350 nm|
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from the P6 microarchitecture.
From Pentium Pro to Pentium III
The P6 core was the sixth generation Intel microprocessor in the x86 line. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).
P6 processors dynamically translate IA-32 instructions into sequences of buffered RISC-like micro-operations, and then analyze and reorder the micro-operations in order to detect parallelizable operations that may be issued to more than one execution unit at once. The Pentium Pro was not the first x86 chip to use this technique — the NexGen Nx586, introduced in 1994, also used it — but it was the first Intel x86 chip to do so.
Some techniques first used in the x86 space in the P6 core include:
- Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
- Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro and early model of the Pentium III(coppermine), and eventually morphed into less than 10-stage pipeline of the Pentium III Tualatin for embedded and mobile market due to energy inefficiency and higher voltage issues that encountered in the predecessor, and then again lengthening the 10- to 12-stage pipeline back to the Pentium M due to facing difficulty increasing clock speed while improving fabrication process can somehow negate some negative impact of higher power consumption on the deeper pipeline design.
- PAE and a wider 36-bit address bus to support 64 GB of physical memory (the linear address space of a process was still limited to 4 GB).
- Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.
- CMOV instructions heavily used in compiler optimization.
- Other new instructions: FCMOV, FCOMI/FCOMIP/FUCOMI/FUCOMIP, RDPMC, UD2.
- New instructions in Pentium II Deschutes core: FXSAVE, FXRSTOR.
- New instructions in Pentium III: SSE.
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). The P6 line of processing cores was succeeded with the NetBurst (P68) architecture which appeared with the introduction of Pentium 4. This was a completely different design based on the use of very long pipelines that favoured high clock speed at the cost of lower IPC, and higher power consumption.
P6 based chips
- Celeron (Covington/Mendocino/Coppermine/Tualatin variants)
- Pentium Pro
- Pentium II Overdrive (a Pentium II chip in the 387 pin Socket 8)
- Pentium II
- Pentium II Xeon
- Pentium III
- Pentium III Xeon
P6 Variant Pentium M
|L1 cache||64KB (32 KB I Cache + 32 KB D cache)|
|L2 cache||512 KB to 2048 KB|
|Created||March 12, 2003|
|Transistors||77M 130 nm (B1, B2)|
|Successor||Enhanced Pentium M|
Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life.
Realizing their new microarchitecture wasn't the best choice for the mobile space, Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a modernized P6 design called the Pentium M:
- Quad-pumped Front Side Bus. With the initial Banias core, Intel adopted the 400 MT/s FSB first used in Pentium 4. The Dothan core moved to the 533 MT/s FSB, following Pentium 4's evolution.
- Larger L1/L2 cache. L1 cache increased from predecessor's 32 KB to current 64 KB in all models. Initially 1 MB L2 cache in the Banias core, then 2 MB in the Dothan core. Dynamic cache activation by quadrant selector from sleep states.
- SSE2 Streaming SIMD (Single Instruction, Multiple Data) Extensions 2 support.
- A 12- or 14-stage instruction pipeline that allows for higher clock speeds.
- Dedicated register stack management.
- Addition of global history, indirect prediction, and loop prediction to branch prediction table. Removal of local prediction.
- Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can result in fewer RISC micro-operations and thus require fewer processor cycles to complete.
The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth. The first Pentium M family processors ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support is required in their kernels.
P6 Variant Enhanced Pentium M
|L1 cache||64 KB|
|L2 cache||1 MB to 2 MB|
2 MB (Xeon)
|Model||Celeron M Series|
|Transistors||151M 65 nm (C0, D0)|
The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the Pentium M's shortcomings by adding:
- SSE3 Support
- Single- and dual-core technology with 2 MB of shared L2 cache (restructuring processor organization)
- Increased FSB speed, with the FSB running at 533 MT/s or 667 MT/s.
- A 12-stage instruction pipeline.
This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
On July 27, 2006, the Core microarchitecture, a derivative of P6, was launched in form of the Core 2 processor. Subsequently, more processors were released with the Core microarchitecture under Core 2, Xeon, Pentium and Celeron brand names. The Core microarchitecture is Intel's final mainstream processor line to use FSB, with all later Intel processors based on Nehalem and later Intel microarchitectures featuring an integrated memory controller and a QPI or DMI bus for communication with the rest of the system. Improvements relative to the Intel Core processors were:
- A 14-stage instruction pipeline that allows for higher clock speeds.
- SSE4.1 support for all Core 2 models manufactured at a 45 nm lithography.
- Support for the 64-bit x86-64 architecture, which was previously only offered by Prescott processors, the Pentium 4 last architectural installment.
- Increased FSB speed, ranging from 533 MT/s to 1600 MT/s.
- Increased L2 cache size, with the L2 cache size ranging from 1 MB to 12 MB (Core 2 Duo processors use a shared L2 cache while Core 2 Quad processors having half of the total cache is shared by each core pair).
- Dynamic Front Side Bus Throttling (some mobile models), where the speed of the FSB is reduced in half, which by extension reduces the processor's speed in half. Thus the processor goes to a low power consumption mode called Super Low Frequency Mode that helps extend battery life.
- Dynamic Acceleration Technology for some mobile Core 2 Duo processors, and Dual Dynamic Acceleration Technology for mobile Core 2 Quad processors. Dynamic Acceleration Technology allows the CPU to overclock one processor core while turning off the one. In Dual Dynamic Acceleration Technology two cores are deactivated and two cores are overclocked. This feature is triggered when an application only uses a single core for Core 2 Duo or up to two cores for Core 2 Quad. The overclocking is performed by increasing the clock multiplier by 1.
While all these chips are technically derivatives of the Pentium Pro, the architecture has gone through several radical changes since its inception.