Talk:x86

Core 2's physical address is 40bit

core 2 has been 40bit ever since woodcrest, even intel's officisl em64t demonstrated it can address up to 1 TB ram. Only older yamhill/ia32E have 36 bit address. — Preceding unsigned comment added by 2601:243:403:E1B0:A54B:6340:AF33:21E7 (talk) 20:16, 12 May 2016 (UTC)

Thank you for your kindness badly! But please do not get me wrong, I do not want to go against with you. But I have to say that Core 2 Solo/Duo/Quad are Core 2 series processors, while Xeon processors are Xeon, even though they share the same microarchitecture (similar internal cores), but they are different things! Core 2 is a general thing, while Xeon is a special, so let not consider the exceptional, I change it back. Computerfann (talk) 11:49, 29 June 2016 (UTC)

Well, another question lying on QPI. Frankly, QPI is not a bus, but a point-to-point link, but similar with HyperTransport, one could also call it as QPI bus. QPI was designed by Intel to take place and extend the capabilities of the traditional and long-term running Front Side Bus. For the first generation of Intel Core i7 processor, the Front Side Bus was replaced and extended by three QPI links, which could further be connected with North Bridge (lack of MCH) or QPI links of other processors. For the first generation of Core i5/i3, the QPI is used only to take place of traditional Front Side Bus, connecting processors core with un-core on the same die, it seems like to wrap the whole parallel Front Side Bus with the serialized QPI link, so there is no change for the addressing policy. Computerfann (talk) 12:07, 29 June 2016 (UTC)

@Jeh:, well, I am very sorry, I should never get involved into this argument. I leave this very problem to you, because I know you are a notable person in this field! Please come to take a look at it, thank you! Computerfannn (talk) 15:16, 7 July 2016 (UTC)

I agree that QPI is not a bus. And I wouldn't call it "QPI bus". It's an interconnect and that word is already in "QPI".

Regarding 36 vs 40 bit, I don't know - I haven't looked at the Intel specs, and I don't have time for it now. Jeh (talk) 18:44, 7 July 2016 (UTC)

@Jeh:, about three months passed! Are you free all the time to look at specs from anywhere (not limited to Intel) to answer this very question? Do please do something useful to improve the quality of the main article! Your best buddy on wiki, if you are a single lady!

I've made that change! Readers, positive readers could find reason from https://communities.intel.com/message/408772#408772. I think this link could be as a source, an official source from definitely Intel, rather than my own! --- Aaron Janagewen 139.210.139.160 (talk) 10:31, 7 October 2016 (UTC)

Mention the x86 assembly language more

The x86 assembly language is only mentioned once in passing in the article, and once again in the "See also" section. I believe it is crucial that it is discussed in the article, and a clear distinction is made between "x86 as instruction set" and "x86 as assembly language".

72.230.215.230 (talk) 00:25, 9 July 2016 (UTC)

So what about the assembly language, as opposed to the machine language/instruction set, needs to be discussed here as opposed to being discussed in x86 assembly language? Guy Harris (talk) 00:45, 9 July 2016 (UTC)

I think the article has wide enough scope as it is. And as Guy noted, we already have the x86 assembly language article.

But an important overriding point for me is this: the "x86 assembly language" isn't really about the processor; it is purely an artifact of software (assembler, disassembler, debugger, etc.) and documentation. Let me put it stronger: As far as the processor is concerned there is no such thing as assembly language, any more than there is C or Java or PHP. There have been x86 assemblers (and disassemblers) that changed some of the opcode mnemonics, used different notation for operand specifiers, even reversed the order of operands (eg MOV src dst instead of MOV dst src). So there is no such thing as the x86 assembly language. This article, on the other hand, is about the processor itself. So I think these are fundamentally different kinds of topics. Jeh (talk) 00:53, 9 July 2016 (UTC)

Well, the assembly language is a tool for coding, while an architecture is the mechanism providing the fundamental resources for coding. Assembly Language might have different styles irrelative with the actual architecture, such as Intel Assembler and GCC Assembler, they both use the different grammar, but do actually assist coding for the same architecture. So emphasising something relative but not substantial tends to be meaningless, and few mentioned is just enough! Rechnerfan (talk) 15:59, 9 July 2016 (UTC)

I find it odd though that the MIPS instruction set page includes a big section devoted to the assembly language. Perhaps because there aren't many different assemblers with distinct syntaxes available for MIPS? 72.230.215.230 (talk) 17:59, 11 July 2016 (UTC)

Probably because there isn't a separate article on the MIPS assembly language, as there is for x86. And no, we're not interested in merging that into here. Jeh (talk) 18:27, 11 July 2016 (UTC)

Virtualization or Virtualisation?

Well, frankly, both are correct. They both are widely used in British and American English, but the former is a little bit more popular! Rechnerfan (talk) 15:51, 9 July 2016 (UTC)

When we're writing about x86, we look at the defining documents of x86. Those are written by AMD and Intel, They use the spelling "virtualization". Wikipedia follows its references. Jeh (talk) 18:25, 11 July 2016 (UTC)

AMD Liano and 64-bit Virtual Address

Well, frankly, AMD Liano has only implemented 40-bit physical addressing bus, even though its core are commonly considered as 10.5h, and sorted into the kind of 10h. No matter K8 or 10h, Hyper Transport unit is an unseparated part of the underlying architecture, but AMD Liano and further APU lack this very thing. So they are different from the real AMD 10h microarchitecture. As to the first generation of AMD APU for desktop, 40-bit physical addressing bus later was succeeded by Bulldozer based APU with fully implementation of 48-bit one.

As to the Virtual Address, shall we mentioned only 48-bit implemented to avoid the ambiguity? As to the AMD64 or x86-64 architecture, expanding 48-bit to the fully 64-bit is not an easy job for the architects, and until this moment, no practical news from AMD or Intel, imply how and when the 48-bit would be expanded or extended to the long expecting 64-bit... Rechnerfan (talk) 16:15, 11 July 2016 (UTC)

You have this backwards. It would be a very easy job "for the architects": Simply follow the model that was used in going from 32 bits to 48 bits - add another two layers of page table. But nobody is "long expecting" 64 bits v.a.s. to happen anytime soon. For now, for the vast majority of users and uses, the biggest benefit of having a 48-bit address space is simply that ASLR now has far more room to play in. Consider that to actually populate (as opposed putting only 32 or 36 bits' worth of stuff in it, but with lots of holes) a 48-bit address space you would have to have 256 TiB of actual storage - some amount of RAM, plus enough disk space to hold the rest. Just because it's paged doesn't mean it doesn't have to have someplace to be stored; paged just means it doesn't all have to be in RAM at once. Jeh (talk) 18:37, 11 July 2016 (UTC)

There is no AMD Bulldozer Processor capable of addressing out of 48-bit physical space

There is no AMD Bulldozer Processor capable of addressing out of 48-bit physical space, so the presumption of 52-bit PAE does not exist, at least for AMD Bulldozer Processors. So I made a change about that! --- Aaron Janagewen — Preceding unsigned comment added by 221.9.18.5 (talk) 12:46, 8 October 2016 (UTC)

Chronology

Generation	First introduced	Prominent consumer CPU brands	Linear/physical address space	Notable (new) features
1st	1978	Intel 8086, Intel 8088 and clones	16-bit / 20-bit	First x86 microprocessors
	1982	Intel 80186, Intel 80188 and clones, NEC V20/V30		Hardware for fast address calculations, fast multiplication and division
2nd		Intel 80286 and clones	16-bit ((14+16)-bit segmented) / 24-bit	MMU, for protected mode and a larger address space
3rd (IA-32)	1985	Intel 80386 and clones, AMD Am386	32-bit ((14+32)-bit segmented) / 32-bit	32-bit instruction set, MMU with paging, PGA132 socket
3rd/4th	1992	Cyrix Cx486SLC, Cyrix Cx486DLC		L1 cache and pipelining introduced into the 386 platform, PGA132 socket
4th (FPU)	1989	Intel 80486 and clones, AMD Am486		RISC-like pipelining, integrated x87 FPU (80-bit), on-chip cache, PGA168 socket
4th/5th	1997	Am5x86, Cyrix 5x86, Pentium OverDrive		Partial Pentium's specification brought into the 486 platform
5th (Superscalar)	1993	Pentium, Pentium MMX, Rise mP6		Superscalar 64-bit databus, faster FPU, MMX (2× 32-bit), Socket 7
5th/6th	1996	AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III-Samuel (2000), VIA C3-Samuel2 / VIA C3-Ezra (2001)		Discrete microarchitecture (µ-op translation)
6th (PAE, speculative execution)	1995	Pentium Pro	32-bit ((14+32)-bit segmented) / 36-bit physical (PAE)	µ-op translation, conditional move instructions, out-of-order register renaming, speculative execution, PAE (Pentium Pro), in-package L2 cache (Pentium Pro), Socket 8
	1997	Pentium II/III, Celeron, Xeon		SSE (2× 64-bit), on-die L2 Cache (Mendocino, Coppermine), SLOT 1 or Socket 370
	1997	AMD K6/2/III, Cyrix III-Joshua (2000)	32-bit ((14+32)-bit segmented) / 32-bit	On-die L2-Cache (K6-III, Cyrix III Joshua), 3DNow!, no PAE support, Super Socket 7 (K6-2)
	2007	Dm&p vortex86	32-bit ((14+32)-bit segmented) / 36-bit	in-order core with high pipeline, deep integrated with sound&graphic unit(SoC), on-chip memory controller, low clock, low power for embedded use.
6th/7th (μ-op fusion)	2003	Pentium M, VIA C7 (2005), Intel Core (2006)	32-bit ((14+32)-bit segmented) / 36-bit physical (PAE)	Optimized for low thermal design power, four pumped FSB
7th (SMT, SMP)	1999	Athlon, Athlon XP		Superscalar FPU, wide design (up to three x86 instr./clock), Slot A or Socket A
	2000	Pentium 4		Deeply pipelined, high frequency, SSE2, hyper-threading, Socket 478
7th/8th (x86-64)	2005	Pentium 4 Prescott F/506/516/5x1/6xx, Celeron D 3x1/3x6/355, Pentium D	64-bit / 36-bit physical	EM64T technology introduced, very deeply pipelined, very high frequency, SSE3, LGA 775 socket, CMP
8th (x86-64)	2003	Athlon 64, Athlon 64 X2 (2005), Sempron (2004), Opteron	64-bit / 40-bit physical	AMD64 processor (excluding 32-bit Sempron), on-die memory controller, HyperTransport, CMP, virtualization (AMD-V) on some models, Socket 754/939/940 or AM2 socket
	2006	Intel Core 2	64-bit / 36-bit physical	Intel 64 processor, low power, multi-core, lower clock frequency, SSE4 (Penryn), wide dynamic execution, µ-op fusion, macro-µ-op fusion, virtualization (Intel VT) on some models
	2007	AMD Phenom, AMD Phenom II (2008)	64-bit / 48-bit physical	Monolithic quad-core, SSE4a, HyperTransport 3, AM2+ or AM3 socket
	2008	VIA Nano	64-bit / 36-bit physical	Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption; very low power; adaptive power management
8th/9th	2008	Intel Core i3, Core i5 and Core i7 (Nehalem/Westmere)	64-bit / 36-bit physical	QuickPath, native memory controller, on-die L3 cache, modular, Intel HD Graphics introduced onto CPU chip (Clarkdale), LGA 1366 (Nehalem) or LGA 1156 socket
		Intel Atom	32-bit ((14+32)-bit segmented) / 36-bit physical	In-order but highly pipelined, very-low-power, some models (Diamondville)with 32-bit (integer CPU), on-die GPU (Penwell, Cedarview)
	2010	AMD FX	64-bit / 48-bit physical	highly pipelined, very-power hungry, extremely high clock, share instruction cache, first consumer octa-core processor, CMT(Clustered Multi-Thread), FMA, OpenCL, support up to 64 socket per chipset.
	2011	AMD APU C, E and Z Series (Bobcat)	64-bit / 36-bit physical	new Out-of-order microarchitecture for low and ultra low power computing, 64-bit (integer CPU), on-die GPU, PCI Express 2.0 bus introduced into processor
		AMD APU A and E Series (Llano)	64-bit / 40-bit physical	on-die GPU, K10 Core with HT bus and DDR2 memory controller removed, PCI Express 2.0 bus introduced into processor, first generation fusion APU, Socket FM1
9th (GPGPU)	2011	AMD APU A Series (Bulldozer, Trinity and later)	64-bit / 48-bit physical	SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU, Socket FM2 or Socket FM2+
		Intel Core i3, Core i5 and Core i7 (Sandy Bridge/Ivy Bridge)	64-bit / 42-bit physical	Internal Ring connection, GPGPU, LGA 1155 socket.
	2013	Intel Core i3, Core i5 and Core i7 (Haswell/Broadwell)	64-bit / 44-bit physical	AVX2, FMA3, TSX, BMI1, and BMI2 instructions, LGA 1150 socket
10th (SoC, MIC)	2013	AMD Jaguar	64-bit / 48-bit physical	harvest cores (quad or octal) with simple microarchitecture, Soc, heavily deployed for game consoles and low power smart devices
	2015/2016	Intel Core i3, Core i5 and Core i7 (Skylake/Kaby Lake/Cannonlake)	64-bit / 46-bit physical	Out-of-order, 64-bit (integer CPU), AVX3, integrated on-die southbridge, integrated on-die x86 MIC array GPU
Others	2000	Transmeta Crusoe, Transmeta Efficeon	32-bit ((14+32)-bit segmented) / 32-bit	VLIW design with x86 emulator, on-die memory controller
	2001	Intel Itanium IA-32 compatibility mode	32-bit ((14+32)-bit segmented) / N/A	EPIC architecture with an on-package engine (pre-2006 chips, later using IA-32 Execution Layer) that provides backward support for most IA-32 applications
	2012	Intel Xeon Phi (Larrabee)	64-bit / 36-bit physical	Many Integrated Cores (62), In-order P54C with x86-64, very wide vector unit, LRBni instructions (8× 64-bit)

Well, this is Aaron Janagewen, I would continue to maintain the above table. Please do not mention the location of the IP addresses that I use anymore, if you are interested in Chinese and/or China, please trouble others, I won't pay for bills of others! Again, and again, Wikipedia is towards the readers all over the world, not bound or limited to some faked learners here. Do not make any trouble any more!119.53.104.217 (talk) 03:02, 10 October 2016 (UTC)