|Transistors||10 nm transistors|
|Instructions||MMX, AES-NI, CLMUL, FMA3|
|Socket||LGA 1151|
Cannonlake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture, expected to be released in the second half of 2017. As a die shrink, Cannonlake is a new process in Intel's "Process-Architecture-Optimization" execution plan as the next step in semiconductor fabrication. Cannonlake will be used in conjunction with Intel 200 Series chipsets, also known as Union Point. The platform as a whole will be named Union Bay.
It has been speculated for a long time that reaching smaller process nodes would become impractical, leading to the end of Moore's Law. Intel however believes that it will be possible to reach at least 7 nm, though it will perhaps require use of materials other than silicon, such as indium gallium arsenide (InGaAs).
The successors of the Cannonlake microarchitecture will be Icelake (2018) and Tigerlake (2019), which will represent Architecture and Optimization of the Intel Process-Architecture-Optimization Model.
- 200 Series chipset (Union Point)
- Thermal design power (TDP) up to 95 W (LGA 1151)
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