Talk:x86

Core 2's physical address is 40bit

core 2 has been 40bit ever since woodcrest, even intel's officisl em64t demonstrated it can address up to 1 TB ram. Only older yamhill/ia32E have 36 bit address. — Preceding unsigned comment added by 2601:243:403:E1B0:A54B:6340:AF33:21E7 (talk) 20:16, 12 May 2016 (UTC)

Thank you for your kindness badly! But please do not get me wrong, I do not want to go against with you. But I have to say that Core 2 Solo/Duo/Quad are Core 2 series processors, while Xeon processors are Xeon, even though they share the same microarchitecture (similar internal cores), but they are different things! Core 2 is a general thing, while Xeon is a special, so let not consider the exceptional, I change it back. Computerfann (talk) 11:49, 29 June 2016 (UTC)

Well, another question lying on QPI. Frankly, QPI is not a bus, but a point-to-point link, but similar with HyperTransport, one could also call it as QPI bus. QPI was designed by Intel to take place and extend the capabilities of the traditional and long-term running Front Side Bus. For the first generation of Intel Core i7 processor, the Front Side Bus was replaced and extended by three QPI links, which could further be connected with North Bridge (lack of MCH) or QPI links of other processors. For the first generation of Core i5/i3, the QPI is used only to take place of traditional Front Side Bus, connecting processors core with un-core on the same die, it seems like to wrap the whole parallel Front Side Bus with the serialized QPI link, so there is no change for the addressing policy. Computerfann (talk) 12:07, 29 June 2016 (UTC)

@Jeh:, well, I am very sorry, I should never get involved into this argument. I leave this very problem to you, because I know you are a notable person in this field! Please come to take a look at it, thank you! Computerfannn (talk) 15:16, 7 July 2016 (UTC)

I agree that QPI is not a bus. And I wouldn't call it "QPI bus". It's an interconnect and that word is already in "QPI".

Regarding 36 vs 40 bit, I don't know - I haven't looked at the Intel specs, and I don't have time for it now. Jeh (talk) 18:44, 7 July 2016 (UTC)

@Jeh:, about three months passed! Are you free all the time to look at specs from anywhere (not limited to Intel) to answer this very question? Do please do something useful to improve the quality of the main article! Your best buddy on wiki, if you are a single lady!

I've made that change! Readers, positive readers could find reason from https://communities.intel.com/message/408772#408772. I think this link could be as a source, an official source from definitely Intel, rather than my own! --- Aaron Janagewen 139.210.139.160 (talk) 10:31, 7 October 2016 (UTC)

The Core microarchitecture supports 40-bit physical addresses in some implementations.

As far as I know, none of the "Core 2" implementations of the Core microarchitecture do; Woodcrest is a Xeon, not a Core 2.

See "Physical address sizes in Chronology table" below. Guy Harris (talk) 00:41, 24 October 2016 (UTC)

Yup, you are right! As I have already mentioned in Intel communities that Xeon is not what I focused on! I do appreciate your modification onto that table, alright, good! --- Aaron Janagewen — Preceding unsigned comment added by 119.53.111.125 (talk) 02:23, 25 October 2016 (UTC)

The "Chronology" table

I have preserved the old chronology table (with the "generations" column) in the HAT below, for ease of reference.

In changing it to its present form I:

• Removed the "generations" column, which was completely invented by Wikipedia editors. There is no reliable source for a "generation number" that applies across all of the manufacturers. It may be possible to reference manufacturer-specific "generations" but these seem to me to be more a matter of the mfrs' marketing departments' whims than aids to understanding.
• Removed all of the remaining "rowspan" attributes, because they made reordering the table difficult. These could probably be restored (for the "bits" columns) but since more reorg may happen, now would likely be premature.
• Re-ordered the table in chronological order.
• Made these minor corrections of fact. These are the only changes of factual detail I have made, so accusations that the table now has "lots of wrong data" are clearly unfounded.

Jeh (talk) 03:48, 12 October 2016 (UTC)

Suggestions for future work (other than adding references for all existing claims of fact, which is really really important):

• I'm still not comfortable with the "segment bits" info. This column now indicates the number of bits in a segment index, i.e. the number of entries in the segment descriptor array. Some notes need to be added here like "segmenting does not apply in long mode" (but for those procs, segmenting does apply in legacy mode, and so the "segment bits" are still relevant)
• Should there be columns for max supported clock speed? Max cache size? Max number of cores? Feature size? ...
• It would be nice to be able to show how features introduced in one line are carried, or are not carried, through to following lines. But, a simple implementation would require a massively wide table with a check-box column for each feature. It would get messier if there were cases where not every member of a product family (i.e. one line on the chart) implemented all of the features.

Jeh (talk) 19:53, 12 October 2016 (UTC)

Is this turning into List of x86 microprocessors? Guy Harris (talk) 20:16, 12 October 2016 (UTC)

I think it's a supposed to be a "list of significant x86 developments". We certainly don't need to include every model number described by each row. I hate "list" articles in general because they provide no information to put the list items into context, show how they relate to each other, etc. Put it this way - if an article requires no RSs beyond somebody's product or parts catalog, it's not an encyclopedia article. Jeh (talk) 20:29, 12 October 2016 (UTC)

The previous major version of the "chronology" table (prior to removal the "Generation" column, which was pure WP:OR) is preserved here for reference. Please do not modify it. Click the "Show" link at the right end of this box to view it. Jeh (talk) 13:53, 19 October 2016 (UTC)
The following discussion has been closed. Please do not modify it.
Generation First introduced Prominent consumer CPU brands Linear/physical address space Notable (new) features 1st 1978 Intel 8086, Intel 8088 and clones 16-bit / 20-bit First x86 microprocessors 1982 Intel 80186, Intel 80188 and clones, NEC V20/V30 Hardware for fast address calculations, fast multiplication and division 2nd Intel 80286 and clones 16-bit ((14+16)-bit segmented) / 24-bit MMU, for protected mode and a larger address space 3rd (IA-32) 1985 Intel 80386 and clones, AMD Am386 32-bit ((14+32)-bit segmented) / 32-bit 32-bit instruction set, MMU with paging, PGA132 socket 3rd/4th 1992 Cyrix Cx486SLC, Cyrix Cx486DLC L1 cache and pipelining introduced into the 386 platform, PGA132 socket 4th (FPU) 1989 Intel 80486 and clones, AMD Am486 RISC-like pipelining, integrated x87 FPU (80-bit), on-chip cache, PGA168 socket 4th/5th 1997 Am5x86, Cyrix 5x86, Pentium OverDrive Partial Pentium's specification brought into the 486 platform 5th (Superscalar) 1993 Pentium, Pentium MMX, Rise mP6 Superscalar 64-bit databus, faster FPU, MMX (2× 32-bit), Socket 7 5th/6th 1996 AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III-Samuel (2000), VIA C3-Samuel2 / VIA C3-Ezra (2001) Discrete microarchitecture (µ-op translation) 6th (PAE, speculative execution) 1995 Pentium Pro 32-bit ((14+32)-bit segmented) / 36-bit physical (PAE) µ-op translation, conditional move instructions, out-of-order register renaming, speculative execution, PAE (Pentium Pro), in-package L2 cache (Pentium Pro), Socket 8 1997 Pentium II/III, Celeron, Xeon SSE (2× 64-bit), on-die L2 Cache (Mendocino, Coppermine), SLOT 1 or Socket 370 1997 AMD K6/2/III, Cyrix III-Joshua (2000) 32-bit ((14+32)-bit segmented) / 32-bit On-die L2-Cache (K6-III, Cyrix III Joshua), 3DNow!, no PAE support, Super Socket 7 (K6-2) 2007 Dm&p vortex86 32-bit ((14+32)-bit segmented) / 36-bit in-order core with high pipeline, deep integrated with sound&graphic unit(SoC), on-chip memory controller, low clock, low power for embedded use. 6th/7th (μ-op fusion) 2003 Pentium M, VIA C7 (2005), Intel Core (2006) 32-bit ((14+32)-bit segmented) / 36-bit physical (PAE) Optimized for low thermal design power, four pumped FSB 7th (SMT, SMP) 1999 Athlon, Athlon XP Superscalar FPU, wide design (up to three x86 instr./clock), Slot A or Socket A 2000 Pentium 4 Deeply pipelined, high frequency, SSE2, hyper-threading, Socket 478 7th/8th (x86-64) 2005 Pentium 4 Prescott F/506/516/5x1/6xx, Celeron D 3x1/3x6/355, Pentium D 64-bit / 36-bit physical EM64T technology introduced, very deeply pipelined, very high frequency, SSE3, LGA 775 socket, CMP 8th (x86-64) 2003 Athlon 64, Athlon 64 X2 (2005), Sempron (2004), Opteron 64-bit / 40-bit physical AMD64 processor (excluding 32-bit Sempron), on-die memory controller, HyperTransport, CMP, virtualization (AMD-V) on some models, Socket 754/939/940 or AM2 socket 2006 Intel Core 2 64-bit / 36-bit physical Intel 64 processor, low power, multi-core, lower clock frequency, SSE4 (Penryn), wide dynamic execution, µ-op fusion, macro-µ-op fusion, virtualization (Intel VT) on some models 2007 AMD Phenom, AMD Phenom II (2008) 64-bit / 48-bit physical Monolithic quad-core, SSE4a, HyperTransport 3, AM2+ or AM3 socket 2008 VIA Nano 64-bit / 36-bit physical Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption; very low power; adaptive power management 8th/9th 2008 Intel Core i3, Core i5 and Core i7 (Nehalem/Westmere) 64-bit / 40-bit physical QuickPath, native memory controller, on-die L3 cache, modular, Intel HD Graphics introduced onto CPU chip (Clarkdale), LGA 1366 (Nehalem) or LGA 1156 socket Intel Atom 32-bit ((14+32)-bit segmented) / 36-bit physical In-order but highly pipelined, very-low-power, some models (Diamondville)with 32-bit (integer CPU), on-die GPU (Penwell, Cedarview) 2010 AMD FX 64-bit / 52-bit physical highly pipelined, very-power hungry, extremely high clock, share instruction cache, first consumer octa-core processor, CMT(Clustered Multi-Thread), FMA, OpenCL, support up to 64 socket per chipset. 2011 AMD APU C, E and Z Series (Bobcat) 64-bit / 36-bit physical Out-of-order, 64-bit (integer CPU), on-die GPU; low power (Bobcat), Socket FM1 (Desktop) AMD APU A and E Series (Llano) 64-bit / 48-bit physical on-die GPU, first generation fusion APU 9th (GPGPU) 2011 AMD APU A Series (Bulldozer, Trinity and later) SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU, Socket FM2 or Socket FM2+ Intel Core i3, Core i5 and Core i7 (Sandy Bridge/Ivy Bridge) 64-bit / 42-bit physical Internal Ring connection, GPGPU, LGA 1155 socket. 2013 Intel Core i3, Core i5 and Core i7 (Haswell/Broadwell) 64-bit / 44-bit physical AVX2, FMA3, TSX, BMI1, and BMI2 instructions, LGA 1150 socket 10th (SoC, MIC) 2015/2016 Intel Core i3, Core i5 and Core i7 (Skylake/Kaby Lake/Cannonlake) 64-bit / 46-bit physical Out-of-order, 64-bit (integer CPU), AVX3, integrated on-die southbridge, integrated on-die x86 MIC array GPU Others 2000 Transmeta Crusoe, Transmeta Efficeon 32-bit ((14+32)-bit segmented) / 32-bit VLIW design with x86 emulator, on-die memory controller 2001 Intel Itanium IA-32 compatibility mode 32-bit ((14+32)-bit segmented) / N/A EPIC architecture with an on-package engine (pre-2006 chips, later using IA-32 Execution Layer) that provides backward support for most IA-32 applications 2012 Intel Xeon Phi (Larrabee) 64-bit / 36-bit physical Many Integrated Cores (62), In-order P54C with x86-64, very wide vector unit, LRBni instructions (8× 64-bit)

Pentium MMX in Chronology table

In the "Chronology" table, it says the Pentium MMX debuted in 1993, but the P5 (microarchitecture) article says it came out on October 22, 1996 and that date has a citation. Seems like it should be changed. Bumm13 (talk) 22:40, 20 October 2016 (UTC)

Thanks for the catch! Let's try to find some other sources to confirm. Jeh (talk) 00:33, 21 October 2016 (UTC)

The issue there might be that all P5s are being lumped together in that entry; the original P5 came out in 1993, but the MMX processors came out later. If the MMX deserves an entry of its own - which, as it was, I think, one of the early "multimedia" instruction sets, it might - that entry would have 1996. Guy Harris (talk) 01:25, 21 October 2016 (UTC)

Physical address sizes in Chronology table

The Core microarchitecture can support up to 40-bit physical addresses, e.g. in the Xeon 7200/7300 series, but not all processors with cores with that architecture do, e.g. the Core 2 desktop/laptop processors and the Xeon 5100 series.

So should the physical address space column for a given microarchitecture give only the largest physical address supported by any implementation of that microarchitecture (with a citation), or should it give all the different physical address sizes for different implementations (with citations)? I made the current row for "Core 2" do the latter 1) to show that there are Core microarchitecture chips with 36-bit physical addresses and Core microarchitecture chips with 40-bit physical addresses and 2) to show what it looks like. I think "what it looks like" is "a bit cluttered", so perhaps the column should just show the maximum physical address size. Guy Harris (talk) 00:37, 24 October 2016 (UTC)

I think to emphasise the general one is much better than the special one! Core Microarchitecture is the processor microarchitecture, an abstract model. But the physical addressing is the real implementation of the processor chip rather than its underlying core to implement x86 architecture. So confusing those two different things would not result in anything good. --- Aaron Janagewen