Epyc

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AMD Epyc
File:AMD EPYC logo.png
General information
LaunchedJune 2017
Marketed byAMD
Designed byAMD
Common manufacturer(s)
Performance
Max. CPU clock rate2.7 GHz to 3.9 GHz
Architecture and classification
Technology node14 nm to 7 nm
MicroarchitectureZen
Zen 2
Instruction setAMD64/x86-64, MMX(+), SSE1, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AES, CLMUL, AVX, AVX2, FMA3, CVT16/F16C, ABM, BMI1, BMI2, SHA
Physical specifications
Cores
  • up to 128 cores/256 threads on dual-socket systems
Socket(s)
Products, models, variants
Core name(s)
  • Naples
  • Rome
Brand name(s)
  • Epyc
History
Predecessor(s)Opteron

Epyc is a brand of x86-64 microprocessors introduced in June 2017[1], designed and marketed by AMD based on the company's Zen microarchitecture. They are specifically targeted for the server and embedded system markets. Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-graded features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. It also supports multi-chip and dual-socket system configurations through the Infinity Fabric interchip interconnect.

History

In March 2017, AMD announced a server platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May.[2] That June, AMD officially launched Epyc by releasing the Epyc 7001 series processors.[3] Two years later, in August 2019, the Epyc 7002 series processors based on the Zen 2 microarchitecture released, bringing much better performance and double the cores compared to their predecessors.

The future Zen 3 based Epyc microarchitecture will be codenamed "Milan".[4]

AMD EPYC CPU Codenames[5]
Gen Year Name Cores
1st 2017 Naples 32 x Zen 1
2nd 2019 Rome 64 x Zen 2
3rd 2020 Milan ? x Zen 3
4th ? Genoa ? x Zen 4
5th ? ? ? x Zen 5

Design

The platform includes one- and two-socket systems. In multi-processor configurations, two Epyc CPUs communicate via AMD's Infinity Fabric.[6] Each server chip supports 8 channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes from each are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.[7] All Epyc processors are composed of four eight-core Zeppelin dies (the same die as found in Ryzen processors) in a multi-chip module, with the varying product core counts produced by symmetrically disabling cores of each core complex on each Zeppelin die.[8][9]

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some unavailable features require additional controller chips to make them available on the system.

The first generation of Epyc microprocessors were manufactured by GlobalFoundries using a 14 nm FinFET process licensed from Samsung Electronics.[10] Epyc 2 will be manufactured by TSMC using a 7 nm FinFET process.[11]

Reception

Initial reception to Epyc was generally positive.[12] Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.[12]

Features

CPU features table

Products

Server

First generation Epyc (Naples)


Common features of EPYC 7001 series CPUs:

  • Socket: SP3.
  • All the CPUs support ECC DDR4-2666 in octa-channel mode (7251 supports only DDR4-2400).
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 128 PCIe 3.0 lanes.
  • Fabrication process: GlobalFoundries 14LP.
Model[i] Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[ii] 		Release Embedded
options[iii]
Base Boost Date Price
(USD)
All–core Max
7251[13][14] 8 (16) 2.1 2.9 2.9 32 MB 120 W 4 × CCD 8 × 1 Jun 2017[15] $475 Yes
7261[13][16] 2.5 64 MB 155/170 W Jun 2018[17] $570 Yes
7281[13][14] 16 (32) 2.1 2.7 2.7 32 MB 8 × 2 Jun 2017[15] $650 Yes
7301[13][14] 2.2 64 MB $800 Yes
7351P[13][14] 2.4 2.9 2.9 $750 735P
7351[13][14] $1,100 Yes
7371[13][18] 3.1 3.6 3.8 200 W Nov 2018[19] $1,550 Yes
7401P[13][14] 24 (48) 2.0 2.8 3.0 155/170 W 8 × 3 Jun 2017[15] $1,075 740P
7401[13][14] $1,850 Yes
7451[13][14] 2.3 2.9 3.2 180 W $2,400 Yes
7501[13][14] 32 (64) 2.0 2.6 3.0 155/170 W 8 × 4 $3,400 Yes
7551P[13][14] 2.55 180 W $2,100 755P
7551[13][14] $3,400 Yes
7571[20][21] 2.2 3.0 200 W Nov 2018 OEM/AWS Un­known
7601[13][14] 2.7 3.2 180 W Jun 2017[15] $4,200 Yes
  1. ^ Models with "P" suffixes are uniprocessors, only available as single socket configuration.
  2. ^ Core Complexes (CCX) × cores per CCX
  3. ^ Epyc embedded 7001 series models have identical specifications as Epyc 7001 series.

Second generation Epyc (Rome)

First generation Epyc processor

In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture.[22] The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket.[23] The 7 nm "Rome" is manufactured by TSMC.[11] It was released on August 7, 2019.[24]

Common features of these CPUs:

  • Codenamed "Rome"
  • Zen 2 microarchitecture
  • TSMC 7 nm process
  • SP3 Socket
  • 128 PCIe lanes
  • Memory support: eight-channel DDR4-3200
Model Release
date 		Price
(USD) 		Fab Chiplets Cores
(threads) 		Core
config[i] 		Clock rate (GHz) Cache Socket
&
Scaling 		TDP
Base Boost L1 L2 L3
7232P August 7,
2019 		$450 TSMC
7FF 		2 × CCD
1 × I/OD 		8 (16) 4 × 2 3.1 3.2 32 KB inst.
32 KB data
(per core) 		512 KB
(per core) 		32 MB
(8 MB per CCX) 		SP3
1P 		120 W
7302P $825 4 × CCD
1 × I/OD 		16 (32) 8 × 2 3 3.3 128 MB
(16 MB per CCX) 		155 W
7402P $1250 24 (48) 8 × 3 2.8 3.35 180 W
7502P $2300 32 (64) 8 × 4 2.5 3.35
7702P $4425 8 × CCD
1 × I/OD 		64 (128) 16 × 4 2 3.35 256 MB
(16 MB per CCX) 		200 W
7252 $475 2 × CCD
1 × I/OD 		8 (16) 4 × 2 3.1 3.2 64 MB
(16 MB per CCX) 		SP3
(up to) 2P 		120 W
 7262 $575 4 × CCD
1 × I/OD 		8 × 1 3.2 3.4 128 MB
(16 MB per CCX) 		155 W
7272 $625 2 × CCD
1 × I/OD 		12 (24) 4 × 3 2.9 3.2 64 MB
(16 MB per CCX) 		120 W
7282 $650 16 (32) 4 × 4 2.8 3.2
7302 $978 4 × CCD
1 × I/OD 		8 × 2 3 3.3 128 MB
(16 MB per CCX) 		155 W
7352 $1350 24 (48) 8 × 3 2.3 3.2
7402 $1783 8 × 3 2.8 3.35 180 W
7452 $2025 32 (64) 8 × 4 2.35 3.35 155 W
7502 $2600 8 × 4 2.5 3.35 180 W
7532 $3350 8 × CCD
1 × I/OD 		16 × 2 2.4 3.3 256 MB
(16 MB per CCX) 		200 W
7542 $3400 4 × CCD
1 × I/OD 		8 × 4 2.9 3.4 128 MB
(16 MB per CCX) 		225 W
7552 $4025 6 × CCD
1 × I/OD 		48 (96) 12 × 4 2.2 3.3 192 MB
(16 MB per CCX) 		200 W
7642 $4775 8 × CCD
1 × I/OD 		16 × 3 2.3 3.3 256 MB
(16 MB per CCX) 		225 W
7662 $6150 64 (128) 16 × 4 2 3.3 225 W
7702 $6450 2 3.35 200 W
7742 $6950 2.25 3.4 225 W
7H12 September 18, 2019 2.6 3.3 280 W
7F32 April 14, 2020[25] $2100 4 × CCD
1 × I/OD 		8 (16) 8 × 1 3.7 3.9 128 MB
(16 MB per CCX) 		180 W
7F52 $3100 8 × CCD
1 × I/OD 		16 (32) 16 × 1 3.5 3.9 256 MB
(16 MB per CCX) 		240 W
7F72 $2450 6 × CCD
1 × I/OD 		24 (48) 12 × 2 3.2 3.7 192 MB
(16 MB per CCX) 		240 W
  1. ^ Core Complexes (CCX) × cores per CCX

Third generation Epyc (Milan)

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture.[26] Milan chips will use Socket SP3, with up to 64 cores on die, and support eight DDR4 SDRAM and PCIe 4.0 channels.[26] It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.[26]

Embedded

First generation Epyc (Snowy Owl)

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.[27]

Common features of EPYC Embedded 3000 series CPUs:

  • Socket: SP4 (31xx and 32xx models use SP4r2 package).
  • All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
  • Fabrication process: GlobalFoundries 14 nm.
Model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i] 		Release
date
Base Boost
All-core Max
3101[28] 4 (4) 2.1 2.9 2.9 8 MB 35 W 1 x CCD 1 × 4 Feb 2018
3151[28] 4 (8) 2.7 16 MB 45 W 2 × 2
3201[28] 8 (8) 1.5 3.1 3.1 30 W 2 × 4
3251[28] 8 (16) 2.5 55 W
3255[29] 25–55 W Dec 2018
3301[28] 12 (12) 2.0 2.15 3.0 32 MB 65 W 2 x CCD 4 × 3 Feb 2018
3351[28] 12 (24) 1.9 2.75 60–80 W
3401[28] 16 (16) 1.85 2.25 85 W 4 × 4
3451[28] 16 (32) 2.15 2.45 80–100 W
  1. ^ Core Complexes (CCX) × cores per CCX

Chinese variants

A variant created for the Chinese server market by a AMD–Chinese joint venture is the Hygon Dhyana system on a chip.[30][31] It is noted to be a variant of the AMD EPYC, and is so similar that "there is little to no differentiation between the chips".[30] It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".[31] Later Benchmarks showed that certain floating point instructions are performing worse and AES is disabled, probably to comply with US export restrictions.[32]

References

  1. ^ Cutress, Ian. "Computex 2017: AMD Press Event Live Blog". www.anandtech.com.
  2. ^ Kampman, Jeff (16 May 2017). "AMD's Naples datacenter CPUs will make an Epyc splash". Tech Report. Retrieved 16 May 2017.
  3. ^ Cutress, Ian (20 June 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". Anandtech. Retrieved 12 July 2017.
  4. ^ https://www.anandtech.com/show/14568/an-interview-with-amds-forrest-norrod-naples-rome-milan-genoa
  5. ^ AMD Confirms Zen 4 EPYC Codename, and Elaborates on Frontier Supercomputer CPU. AnandTech.
  6. ^ Kampman, Jeff (7 March 2017). "AMD's Naples platform prepares to take Zen into the datacenter". Tech Report. Retrieved 7 March 2017.
  7. ^ Cutress, Ian (7 March 2017). "AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2". Anandtech. Retrieved 7 March 2017.
  8. ^ Shrout, Ryan (20 June 2017). "AMD EPYC 7000 Series Data Center Processor Launch – Gunning for Xeon | Architectural Outlook". www.pcper.com. Retrieved 9 August 2019.
  9. ^ Morgan, Timothy Prickett (May 17, 2017). "AMD Disrupts The Two-Socket Server Status Quo". www.nextplatform.com.
  10. ^ Morris, John (March 13, 2018). "Inside GlobalFoundries' long road to the leading edge". ZDNet. Retrieved 17 July 2019.
  11. ^ a b Smith, Ryan (July 26, 2018). "AMD "Rome" EPYC CPUs to Be Fabbed By TSMC". AnandTech. Retrieved 18 June 2019.
  12. ^ a b De Gelas, Johan; Cutress, Ian (11 July 2017). "Sizing Up the Servers: Intel's Skylake-SP Xeon vs AMD's EPYC 7000". Anandtech. Retrieved 11 July 2017.
  13. ^ a b c d e f g h i j k l m n "AMD EPYC 7000 Series Processors" (PDF). AMD. January 2019. Retrieved March 25, 2023.
  14. ^ a b c d e f g h i j k l Cutress, Ian (June 20, 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". AnandTech. Retrieved June 21, 2017.
  15. ^ a b c d Kennedy, Patrick (May 16, 2017). "AMD EPYC New Details on the Emerging Server Platform". ServeTheHome. Retrieved May 16, 2017.
  16. ^ "AMD EPYC 7261 - PS7261BEV8RAF". CPU-World. March 26, 2023.
  17. ^ Kennedy, Patrick (October 31, 2018). "AMD EPYC 7261 8 Core CPU Quietly Launched L3 Cache Monster". ServeTheHome. Retrieved March 28, 2023.
  18. ^ "AMD EPYC 7371 - PS7371BDVGPAF". CPU-World. March 26, 2023.
  19. ^ "New AMD-Powered Supercomputers Unleash Discovery and Accelerate Innovation" (Press release). AMD. November 13, 2018. Retrieved March 28, 2023.
  20. ^ "AMD EPYC 7571 - PS7571BDVIHAF". CPU-World. March 25, 2023.
  21. ^ Larabel, Michael (November 7, 2018). "A Look At The AMD EPYC Performance On The Amazon EC2 Cloud". Phoronix. Retrieved March 28, 2023.
  22. ^ "AMD Takes High-Performance Datacenter Computing to the Next Horizon". AMD. Retrieved 2018-12-06.
  23. ^ Gordon Mah Ung (2018-11-07). "What AMD's 64-core 'Rome' server CPU tells us about Ryzen 2". PCWorld. Retrieved 2018-11-08.
  24. ^ "2nd Gen AMD EPYC™ Processors Set New Standard for the Modern Datacenter with Record-Breaking Performance and Significant TCO Savings". AMD. August 7, 2019. Retrieved August 8, 2019.
  25. ^ "New 2nd Gen AMD EPYC™ Processors Redefine Performance for Database, Commercial HPC and Hyperconverged Workloads". AMD. April 14, 2020.
  26. ^ a b c Alcorn, Paul (5 October 2019). "AMD dishes on Zen 3 and Zen 4 architecture, Milan and Genoa roadmap". Tom's Hardware. Retrieved 5 October 2019.
  27. ^ Alcorn, Paul (21 February 2018). "AMD Launches Ryzen Embedded V1000, EPYC Embedded 3000 Processors". tom's HARDWARE. Retrieved 5 April 2018.
  28. ^ a b c d e f g h "Product Brief: AMD EPYC Embedded 3000 Family" (PDF). AMD. 2018. Retrieved March 26, 2023.
  29. ^ "AMD EPYC Embedded 3255 - PE3255BGR88AF". CPU-World. March 26, 2023.
  30. ^ a b Alcorn, Paul (6 July 2018). "China Finds Zen: Begins Production Of x86 Processors Based On AMD's IP". Tom's Hardware. Retrieved 9 July 2018.
  31. ^ a b Larabel, Michael (9 June 2018). "Hygon Dhyana: Chinese x86 Server CPUs Based On AMD Zen". Phoronix. Retrieved 9 July 2018.
  32. ^ Cutress, Ian. "Testing a Chinese x86 CPU: A Deep Dive into Zen-based Hygon Dhyana Processors". www.anandtech.com.
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