List of AMD CPU microarchitectures
AMD has not used K-nomenclature codenames (which originally stood for Kryptonite) in official AMD documents and press releases since the beginning of 2005, when K8 described the Athlon 64 processor family. AMD now refers to the codename K8 processors as the Family 0Fh processors. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0F(h) (where the h represents hexadecimal numbering) equals the decimal number 15, and 10(h) equals the decimal number 16. (The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and Family XXh identifier number.)
|15||0Fh||K8 / Hammer|
The Family hexadecimal identifier number can be determined for a particular processor using the freeware system profiling application CPU-Z, which shows the Family number in the Ext. Family field of the application, as can be seen on various screenshots on the CPU-Z Validator World Records website.
- AMD K5 - AMD's first original x86 microarchitecture. The K5 was based on the AMD Am29k micro architecture with the addition of an x86 decoder. Although the design was similar in idea to a Pentium Pro, the actual performance was more like that of a Pentium.
- AMD K6 - The K6 was not based on the K5 and was instead based on the Nx686 processor that was being designed by NexGen when that company was bought by AMD. The K6 was generally pin-compatible with the Intel Pentium (unlike NexGen's existing processors).
- AMD K7 Athlon - Microarchitecture of the AMD Athlon classic and Athlon XP microprocessors. Was a very advanced design for its day.
- AMD K8 Hammer - Also known as AMD Family 0Fh. Based on the K7 but was extended to 64 bits, added an integrated memory controller, HyperTransport communication fabric, L2 cache sizes up to 1 MB (1128 KB total cache), and SSE2. Later K8 added SSE3. The K8 was the first mainstream Windows-compatible 64-bit microprocessor and was released April 22, 2003. K8 replaced the traditional front side bus with a HyperTransport communication fabric. SledgeHammer was the first design which implemented it.
- AMD Family 10h (K10) - Based on the K8 microarchitecture. Shared Level 3 Cache, 128-bit floating point units, AMD-V Nested Paging virtualization, and HyperTransport 3.0 are introduced. Barcelona was the first design which implemented it.
- AMD Family 11h - combined elements of K8 and K10 designs for Turion X2 Ultra / Puma mobile platform
- AMD Fusion Family 12h - Based on the 10h/K10 design. Includes CPU cores, GPU and Northbridge in the same chip. Llano was the first design which implemented it. Fusion was later re-branded as the APU.
- AMD Bobcat Family 14h - a new distinct line, which is aimed in the 1 W to 10 W low power microprocessor category. Ontario and Zacate were the first designs which implemented it.
- AMD Bulldozer Family 15h - the successor of 10h/K10. Bulldozer is designed for processors in the 10 to 220W category, implementing XOP, FMA4 and CVT16 instruction sets. Orochi was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h.
- AMD Piledriver Family 15h (2nd-gen) - successor to Bulldozer. CPUID model numbers are 02h (earliest "Vishera" Piledrivers) and 10h-1Fh.
- AMD Steamroller Family 15h (3rd-gen) - third-generation Bulldozer derived core. CPUID model numbers are 30h-3Fh.
- AMD Excavator Family 15h (4th-gen) - fourth-generation Bulldozer derived core. CPUID model numbers are 60h-6Fh, later updated revisions have model numbers 70h-7Fh.
- AMD Zen - the successor to the Bulldozer derived cores. Included in the Ryzen CPU line.
- AMD Am2900 - Bit-slice architecture designed in 1975.
- AMD Am29000 - Popular line of 32-bit RISC microprocessors and microcontrollers.
- AMD K12 - ARM64/ARMv8-A