Zero instruction set computer

In computer science, ZISC stands for Zero Instruction Set Computer, which refers to a chip technology based on pure pattern matching and absence of (micro-)instructions in the classical sense. The ZISC acronym alludes to the previously developed RISC (Reduced Instruction Set Computer) technology.

ZISC is a technology based on ideas from artificial neural networks and massively hardwired parallel processing. This concept was invented by Guy Paillet.^{[citation needed]} It was inspired by his collaboration with Pr. Carlo Rubbia's team (Physics Nobel Prize Laureate 1984 - UA1 CERN Geneva) for parallel processing, and with Pr. Leon N. Cooper (Physics Nobel Prize Laureate 1972 - Brown University RI.- Nestor Inc) in the early 90's around the RCE (Restricted Coulomb Energy), a neural network model published by Pr. Leon N. Cooper et al. (1982). RCE was inspired by Pr. Bruce Batchelor's (Cardiff University UK) book "Practical Approach to Pattern Classification", especially the "compound classifier".^{[citation needed]}

Guy brought the overall architecture concept in 1993 to the IBM Paris Semiconductor Laboratory^{[citation needed]}, at that time directed by Bernard Denis. The ZISC36 was the first chip developed by Guy Paillet (independent inventor^{[citation needed]}) and Dr. Pascal Tannhof scientist leader of a team of IBM engineers. The first generation of ZISC chip contains 36 independent cells that can be thought of as neurons or parallel processors. Each of these can compare an input vector ^{[disambiguation needed]} of up to 64 bytes with a similar vector stored in the cell's memory: if the input vector matches the vector in the cell's memory, the cell "fires". The output signal contains either the number of the cell that had a match or the "no matches occurred" indicator.

The parallelism is the key to the speed of ZISC systems, which eliminate the step of serial loading and comparing the pattern for each location. Another key factor is ZISC's scalability: a ZISC network can be expanded by adding more ZISC devices without suffering a decrease in recognition speed^{[citation needed]} - networks with 10,000 or more cells might become common. Today's ZISC chip contains 78 neurons per chip and can find a match among 1,000,000 patterns in one second operating at less than 50 MHz.^{[citation needed]}

In August 2007, Anne Menendez and Guy Paillet released the CM1K (CogniMem 1K) which is an evolution of ZISC78 using 1024 neurons to classify an input vector of 256 bytes in up to 10 microseconds^{[citation needed]}. CM1K semiconductor technology is 0.13 micrometres with a die size of 8x8 mm.

Practical uses of ZISC/CogniMem technology focus on pattern recognition, information retrieval (data mining), security and similar tasks.

External links

US Patent for ZISC hardware, issued to IBM/G.Paillet on April 15, 1997
Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems by K. Madani, G. de Trémiolles, and P. Tannhof
From CISC to RISC to ZISC by S. Liebman on lsmarketing.com
Neural Networks on Silicon at aboutAI.net
Zero instruction set computer at Curlie

See also

External links