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Knights Landing will be built using up to 72 [[Airmont (microarchitecture)|Airmont]] (Atom) cores with four threads per core,<ref>http://wccftech.com/intel-xeon-phi-knights-landing-features-integrated-memory-500-gbs-bandwidth-ddr4-memory-support-architecture-detailed/</ref><ref>{{citation |url=http://www.extremetech.com/extreme/171678-intel-unveils-72-core-x86-knights-landing-cpu-for-exascale-supercomputing |title=Intel unveils 72-core x86 Knights Landing CPU for exascale supercomputing |date=26 November 2013 |author=Sebastian Anthony |publisher= [[ExtremeTech]]}}</ref> support for up to 384&nbsp;GB of DDR4 RAM and 8&ndash;16&nbsp;GB of stacked 3D MCDRAM. Each core will have two 512-bit vector units and will support AVX-512F (AVX3.1) SIMD instructions with Intel AVX-512 Conflict Detection Instructions (CDI), Intel AVX-512 Exponential and Reciprocal Instructions (ERI), and Intel AVX-512 Prefetch Instructions (PFI), along with Intel's full x86 instruction set except [[Transactional Synchronization Extensions|TSX]].<ref>{{citation |url=http://software.intel.com/en-us/blogs/2013/avx-512-instructions |title=AVX-512 Instructions |date=23 July 2013 |author=James Reinders |publisher= [[Intel]]}}</ref> Knights Landing's TDP will range from 160 to 215&nbsp;W.{{Citation needed|date=February 2014}}
Knights Landing will be built using up to 72 [[Airmont (microarchitecture)|Airmont]] (Atom) cores with four threads per core,<ref>http://wccftech.com/intel-xeon-phi-knights-landing-features-integrated-memory-500-gbs-bandwidth-ddr4-memory-support-architecture-detailed/</ref><ref>{{citation |url=http://www.extremetech.com/extreme/171678-intel-unveils-72-core-x86-knights-landing-cpu-for-exascale-supercomputing |title=Intel unveils 72-core x86 Knights Landing CPU for exascale supercomputing |date=26 November 2013 |author=Sebastian Anthony |publisher= [[ExtremeTech]]}}</ref> support for up to 384&nbsp;GB of DDR4 RAM and 8&ndash;16&nbsp;GB of stacked 3D MCDRAM. Each core will have two 512-bit vector units and will support AVX-512F (AVX3.1) SIMD instructions with Intel AVX-512 Conflict Detection Instructions (CDI), Intel AVX-512 Exponential and Reciprocal Instructions (ERI), and Intel AVX-512 Prefetch Instructions (PFI), along with Intel's full x86 instruction set except [[Transactional Synchronization Extensions|TSX]].<ref>{{citation |url=http://software.intel.com/en-us/blogs/2013/avx-512-instructions |title=AVX-512 Instructions |date=23 July 2013 |author=James Reinders |publisher= [[Intel]]}}</ref> Knights Landing's TDP will range from 160 to 215&nbsp;W.{{Citation needed|date=February 2014}}

==={{anchor|Knights Hill}}Knights Hill===
Code name for the third generation MIC architecture. Intel announced the first details at SC14. Manufactured in a 10nm process, 60 to 72 compute cores based on a modified Silvermont Atom core, possibly augmented with 4-way [[hyperthreading]]<ref>{{citation |url=http://goparallel.sourceforge.net/intel-reveals-details-of-next-gen-xeon-phis/ |title=Intel Reveals Details of Next-Gen Xeon Phis, Unveils Fast Fabric |date=20 November 2014 |author=John O'Donnell |publisher= [[Slashdot Media]]}}</ref>. No release was mentioned, but the article notes that this may be two years out.


===Xeon Phi===
===Xeon Phi===

Revision as of 22:52, 29 November 2014

Intel Many Integrated Core Architecture (MIC)
DesignerIntel
Designmanycore extended x86/x64 design
Registers
General-purposeIntel Architecture registers
Floating point512-bit SIMD vector registers

Intel Many Integrated Core Architecture or Intel MIC (pronounced Mick or Mike[1]) is a coprocessor computer architecture developed by Intel incorporating earlier work on the Larrabee many core architecture, the Teraflops Research Chip multicore chip research project, and the Intel Single-chip Cloud Computer multicore microprocessor.

Prototype products codenamed Knights Ferry were announced and released to developers in 2010. The Knights Corner product was announced in 2011 and uses a 22nm process. A second generation product codenamed Knights Landing using a 14nm process was announced in June 2013.

In September 2011, the Texas Advanced Computing Center (TACC) announced it would use Knights Corner cards in their 10-PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of computing power.

At the International Supercomputing Conference (2012, Hamburg), Intel announced the branding of the processor product family as Intel Xeon Phi.[2]

In November 2012, Intel formally announced the first products citing claims of CPU-like versatile programmability, high performance and power efficiency.[3] The Green 500 list placed a system using these new products as the most power efficient computer in the world.[4]

In June 2013, the Tianhe-2 supercomputer at the National Supercomputing Center in Guangzhou (NSCC-GZ) was announced[5] as the world's fastest supercomputer. It utilizes Intel Ivy Bridge-EP Xeon and Xeon Phi processors to achieve 33.86 PetaFLOPS.[6]

History

Background

See also: Larrabee (microarchitecture), Teraflops Research Chip, and Single-chip Cloud Computer

The Larrabee microarchitecture (in development since 2006[7]) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of 4-way multi-threading. Due to the design being intended for GPU as well as general purpose computing the Larrabee chips also included specialised hardware for texture sampling.[8][9] The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010.[10]

Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single Chip Cloud Computer', (prototype introduced 2009.[11]), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores - the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for interchip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.[12]

The Teraflops Research Chip (prototype unveiled 2007[13]) was an experimental 80 core chip with two floating point units per core implementing not x86 but a 96-bit VLIW architecture.[14] The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.[15][16]

Knights Ferry

Intel's MIC prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.[17][18]

The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory,[19] and 8 MB coherent L2 cache (256 kB per core with 32 kB L1 cache), and a power requirement of ~300 W,[19] built at a 45 nm process.[20] In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory.[21] Single board performance has exceeded 750 GFLOPS.[20] The prototype boards only support single precision floating point instructions.[22]

Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.[23]

Knights Corner

The Knights Corner product line is made at a 22 nm process size, using Intel's Tri-gate technology with more than 50 cores per chip, and is Intel's first many-cores commercial product.[17][20]

In June 2011, SGI announced a partnership with Intel to utilize the MIC architecture in its high performance computing products.[24] In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power.[25] According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."[26]

On November 15, 2011, Intel showed an early silicon version of a Knights Corner processor.[27][28]

On June 5, 2012, Intel released open source software and documentation regarding Knights Corner.[29]

In June 2012, Cray announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems.[30][31]

In June 2012, ScaleMP announced it will provide its virtualization software to allows using 'Knight's Corner' chips (branded as 'Xeon Phi') as main processor transparent extension. The virtualization software will allow 'Knight's Corner' to run legacy MMX/SSE code and access unlimited amount of (host) memory without need for code changes.[32]

The Knight's Corner chip was announced as being rebranded as 'Xeon Phi' at the 2012 Hamburg International Supercomputing Conference.[33][34]

Tianhe-2 the world's fastest supercomputer according to the TOP500 list for June and November 2013 utilizes Xeon Phi accelerators based on Knights Corner.

Knights Landing

Code name for the second generation MIC architecture product from Intel.[26] Intel officially first revealed details of its second generation Intel Xeon Phi products on June 17, 2013.[6] Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's 14nm process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth.

Knights Landing will be built using up to 72 Airmont (Atom) cores with four threads per core,[35][36] support for up to 384 GB of DDR4 RAM and 8–16 GB of stacked 3D MCDRAM. Each core will have two 512-bit vector units and will support AVX-512F (AVX3.1) SIMD instructions with Intel AVX-512 Conflict Detection Instructions (CDI), Intel AVX-512 Exponential and Reciprocal Instructions (ERI), and Intel AVX-512 Prefetch Instructions (PFI), along with Intel's full x86 instruction set except TSX.[37] Knights Landing's TDP will range from 160 to 215 W.[citation needed]

Knights Hill

Code name for the third generation MIC architecture. Intel announced the first details at SC14. Manufactured in a 10nm process, 60 to 72 compute cores based on a modified Silvermont Atom core, possibly augmented with 4-way hyperthreading[38]. No release was mentioned, but the article notes that this may be two years out.

Xeon Phi

On June 18, 2012, Intel announced that Xeon Phi will be the brand name used for all products based on their Many Integrated Core architecture.[2][39][40][41][42]

On September 11, 2012, it was announced that a supercomputer called Stampede would be based on the Xeon Phi.[43] Stampede is capable of 10 petaflops.[43]

On November 12, 2012, Intel announced two Xeon Phi coprocessor families which are the Xeon Phi 3100 and the Xeon Phi 5110P.[44][45][46] The Xeon Phi 3100 will be capable of more than 1 teraflops of double precision floating point instructions with 240 GB/sec memory bandwidth at 300 W.[44][45][46] The Xeon Phi 5110P will be capable of 1.01 teraflops of double precision floating point instructions with 320 GB/sec memory bandwidth at 225 W.[44][45][46] The Xeon Phi 7120P will be capable of 1.2 teraflops of double precision floating point instructions with 352 GB/sec memory bandwidth at 300 W.

The Xeon Phi uses the 22 nm process size.[44][45][46] The Xeon Phi 3100 will be priced at under US$2,000 while the Xeon Phi 5110P will have a price of US$2,649 and Xeon Phi 7120 at US$4129.00.[44][45][46] On June 17, 2013, the Tianhe-2 supercomputer was announced[5] by TOP500 as the world's fastest. It uses Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 PetaFLOPS.

An empirical performance and programmability study has been performed by researchers.[47] The authors claim that to achieve high performance Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is still far from reality.

Design

The cores of Intel MIC are based on a modified version of P54C design, used in the original Pentium.[48] The basis of the Intel MIC architecture is to leverage x86 legacy by creating a x86-compatible multiprocessor architecture that can utilize existing parallelization software tools.[20] Programming tools include OpenMP, OpenCL,[49] Cilk/Cilk Plus and specialised versions of Intel's Fortran, C++[50] and math libraries.[51]

Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core[52]), and ultra-wide ring bus connecting processors and memory.

The Knights Corner instruction set documentation is available from Intel.[53][54][55]

Competitors

See also

References

  1. ^ Timothy Prickett Morgan (2012-06-18). "Intel slaps Xeon Phi brand on MIC coprocessors". theregister.co.uk. Retrieved 2014-07-06.
  2. ^ a b Radek (2012-06-18). "Chip Shot: Intel Names the Technology to Revolutionize the Future of HPC - Intel® Xeon® Phi™ Product Family". Intel. Retrieved 2012-12-12.
  3. ^ "Intel Delivers New Architecture for Discovery with Intel® Xeon Phi™ Coprocessors". Intel. Retrieved 21 June 2013.
  4. ^ "The Green500 List - November 2012". Green500. Retrieved 21 June 2013.
  5. ^ a b "TOP500 - June 2013". TOP500 - June 2013. TOP500. Retrieved 18 June 2013.
  6. ^ a b "Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies". Retrieved June 21, 2013.
  7. ^ Charlie Demerjian (3 July 2006), "New from Intel: It's Mini-Cores!", www.theinquirer.net, The Inquirer
  8. ^ Attention: This template ({{cite doi}}) is deprecated. To cite the publication identified by doi:10.1145/1360612.1360617, please use {{cite journal}} (if it was published in a bona fide academic journal, otherwise {{cite report}} with |doi=10.1145/1360612.1360617 instead.
  9. ^ Tom Forsyth, "SIMD Programming with Larrabee" (PDF), www.stanford.edu, Intel
  10. ^ Ryan Smith (25 May 2010), "Intel Kills Larrabee GPU, Will Not Bring a Discrete Graphics Product to Market\", www.anandtech.com, AnandTech
  11. ^ Tony Bradley (3 December 2009), "Intel 48-Core "Single-Chip Cloud Computer" Improves Power Efficiency", www.pcworld.com, PCWorld
  12. ^ "Intel Research : Single-Chip Cloud Computer", techresearch.intel.com, Intel
  13. ^ Ben Ames (11 February 2007), "Intel Tests Chip Design With 80-Core Processor", www.pcworld.com, IDG News
  14. ^ http://www.xbitlabs.com/news/cpu/display/20070212224710.html
  15. ^ "Intel's Teraflops Research Chip" (PDF), download.intel.com, Intel
  16. ^ Anton Shilov (12 February 2007), "Intel Details 80-Core Teraflops Research Chip", www.xbitlabs.com, Xbit laboratories
  17. ^ a b Rupert Goodwins (1 June 2010), "Intel unveils many-core Knights platform for HPC", www.zdnet.co.uk, ZDNet
  18. ^ "Intel News Release : Intel Unveils New Product Plans dor High-Performance Computing", www.intel.com, Intel, 31 May 2010
  19. ^ a b Mike Giles (24 June 2010), "Runners and riders in GPU steeplechase" (PDF), people.maths.ox.ac.uk, pp. 8–10
  20. ^ a b c d Gareth Halfacree (20 June 2011), "Intel pushes for HPC space with Knights Corner", www.thinq.co.uk, Net Communities Limited, UK
  21. ^ "Intel Many Integrated Core Architecture" (PDF), www.many-core.group.cam.ac.uk, Intel, December 2010
  22. ^ Rick Merritt (20 June 2011), "OEMs show systems with Intel MIC chips", www.eetimes.com, EE Times
  23. ^ Tom R. Halfhill (18 July 2011), "Intel Shows MIC Progress", www.linleygroup.com, The Linley Group
  24. ^ Andrea Petrou (20 June 2011), "SGI wants Intel for super supercomputer", news.techeye.net
  25. ^ ""Stampede's" Comprehensive Capabilities to Bolster U.S. Open Science Computational Resources", www.tacc.utexas.edu, Texas Advanced Computing Center, 22 September 2011
  26. ^ a b "Stampede: A Comprehensive Petascale Computing Environment" (PDF). IEEE Cluster 2011 Special Topic. Retrieved November 16, 2011.
  27. ^ Marcus Yam (16 2011), "Intel's Knights Corner: 50+ Core 22nm Co-processor", www.tomshardware.com, Tom's Hardware, retrieved November 16, 2011 {{citation}}: Check date values in: |date= (help)
  28. ^ Sylvie Barak (16 November 2011), "Intel unveils 1 TFLOP/s Knights Corner", www.eetimes.com, EE Times, retrieved November 16, 2011
  29. ^ James Reinders (5 June 2012), Knights Corner: Open source software stack, Intel
  30. ^ Merritt, Rick (8 June 2012), "Cray will use Intel MIC, branded Xeon Phi", www.eetimes.com
  31. ^ Latif, Lawrence (19 June 2012), "Cray to support Intel's Xeon Phi in Cascade clusters", www.theinquirer.net
  32. ^ "ScaleMP vSMP Foundation to Support Intel Xeon Phi", www.ScaleMP.com, ScaleMP, 20 June 2012
  33. ^ Prickett Morgan, Timothy (18 June 2012), "Intel slaps Xeon Phi brand on MIC coprocessors", 222.theregister.co.uk
  34. ^ Intel Corporation (18 June 2012), "Latest Intel(R) Xeon(R) Processors E5 Product Family Achieves Fastest Adoption of New Technology on Top500 List", www.marketwatch.com, Intel(R) Xeon(R) Phi(TM) is the new brand name for all future Intel(R) Many Integrated Core Architecture based products targeted at HPC, enterprise, datacenters and workstations. The first Intel(R) Xeon(R) Phi(TM) product family member is scheduled for volume production by the end of 2012
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  37. ^ James Reinders (23 July 2013), AVX-512 Instructions, Intel
  38. ^ John O'Donnell (20 November 2014), Intel Reveals Details of Next-Gen Xeon Phis, Unveils Fast Fabric, Slashdot Media
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  48. ^ Hruska, Joel (July 30, 2012). "Intel's 50-core champion: In-depth on Xeon Phi". ExtremeTech. Ziff Davis, Inc. Retrieved 2 December 2012.
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