Puma (microarchitecture)

Puma - Family 16h (2nd-gen)
General information
Launched	mid-2014
Discontinued	present
Common manufacturer	AMD;
Performance
Max. CPU clock rate	1.35 GHz to 2.5 GHz
Cache
L1 cache	64 KB per core
L2 cache	1 MB to 2 MB shared
Architecture and classification
Technology node	28 nm
Instruction set	AMD64 (x86-64)
Physical specifications
Cores	2–4;
GPUs	Radeon Rx: 128 cores, 300–800 Mhz
Sockets	Socket AM1; Socket FT3b (BGA-769);
Products, models, variants
Core names	Beema; Mullins;
Brand name	AMD APU;
History
Predecessor	Jaguar - Family 16h

The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.

Design

The Puma cores use the same microarchitecture as Jaguar, and inherits the design:

Out-of-order execution and Speculative execution, up to 4 CPU cores
Two-way integer execution
Two-way 128-bit wide floating-point and packed integer execution
Integer hardware divider
Puma does not feature clustered multi-thread (CMT), meaning that there are no "modules"
Puma does not feature Heterogeneous System Architecture or zero-copy^[2]
32 KiB instruction + 32 KiB data L1 cache per core
1–2 MiB unified L2 cache shared by two or four cores
Integrated single channel memory controller supporting 64bit DDR3L
3.1 mm² area per core

Instruction set support

Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.^[1]

Improvements over Jaguar

19% CPU core leakage reduction at 1.2V^[3]
38% GPU leakage reduction
500 mW reduction in memory controller power
200 mW reduction in display interface power
Chassis temperature aware turbo boost^[4]
Selective boosting according to application needs (intelligent boost)
Support for ARM TrustZone via integrated Cortex-A5 processor
Support for DDR3L-1866 memory^[5]

Puma+

AMD released a revision of Puma core, Puma+, as a part of the Carrizo-L platform in 2015. The differences in the CPU microarchitecture are unclear. Puma+ featured 2 or 4 cores up to 2.5GHz and required the newer FP4 socket.^[6]

Features

APU features table

Processors

Desktop/Mobile (Beema)

Family	Model	Socket	CPU				GPU			TDP	Memory
Family	Model	Socket	Cores	Frequency	Max. Turbo	L2 Cache	Model	Config.	Max. Freq.	TDP	Memory
A8	6410	Socket FT3b	4	2.00 GHz	2.4 GHz	2 MB	Radeon R5	128:?:?	800 MHz	15 W	DDR3L-1866
A6	6310			1.80 GHz	2.4 GHz		Radeon R4		800 MHz	15 W	DDR3L-1866
A4	6250J			2.00 GHz	—		Radeon R3		600 MHz	25 W	DDR3L-1600
A4	6210			1.80 GHz			Radeon R3		600 MHz	15 W
E2	6110			1.50 GHz			Radeon R2		500 MHz	15 W
E1	6010		2	1.35 GHz		1 MB	Radeon R2		350 MHz	10 W	DDR3L-1333

Tablet (Mullins)

Family	Model	CPU				GPU			Power		Memory
Family	Model	Cores	Frequency	Max. Turbo	L2 Cache	Model	Config.	Max. Freq.	TDP	SDP	Memory
A10 Micro	6700T	4	1.2 GHz	2.2 GHz	2 MB	Radeon R6	128:?:?	500 MHz	4.5 W	2.8 W	DDR3L-1333
A6 Micro	6500T		1.2 GHz	1.8 GHz		Radeon R4		401 MHz
A4 Micro	6400T		1.0 GHz	1.6 GHz		Radeon R3		350 MHz
E1 Micro	6200T	2	1.0 GHz	1.4 GHz	1 MB	Radeon R2		300 MHz	3.95 W		DDR3L-1066

References

^ ^a ^b "Software Optimization Guide for Family 16h Processors". AMD. Retrieved August 3, 2013.
^ "AMD launches new Beema, Mullins SoCs". ExtremeTech. 2014-04-29. Retrieved 2014-05-02.
^ Shimpi, Anand. "AMD Beema/Mullins Architecture & Performance Preview". AnandTech. Retrieved 29 April 2014.
^ Shimpi, Anand. "New Turbo Boost, The Lineup and Trustzone". AnandTech. Retrieved 29 April 2014.
^ Woligroski, Don. "Meet The Mullins And Beema Tablet APUs". Toms Hardware. Retrieved 29 April 2014.
^ Cutress, Ian (12 May 2015). "AMD's Carrizo-L APU Unveiled". Anandtech. Retrieved 14 January 2017.

External links

[opti_guide-1] "Software Optimization Guide for Family 16h Processors". AMD. Retrieved August 3, 2013.

[2] "AMD launches new Beema, Mullins SoCs". ExtremeTech. 2014-04-29. Retrieved 2014-05-02.

[3] Shimpi, Anand. "AMD Beema/Mullins Architecture & Performance Preview". AnandTech. Retrieved 29 April 2014.

[4] Shimpi, Anand. "New Turbo Boost, The Lineup and Trustzone". AnandTech. Retrieved 29 April 2014.

[5] Woligroski, Don. "Meet The Mullins And Beema Tablet APUs". Toms Hardware. Retrieved 29 April 2014.

[6] Cutress, Ian (12 May 2015). "AMD's Carrizo-L APU Unveiled". Anandtech. Retrieved 14 January 2017.

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