Talk:X86

"Generation" column again

How did this completely unreferenced bit of stuff-someone-made-up-one-day get back in here?

This is how: https://en.wikipedia.org/w/index.php?title=X86&type=revision&diff=844673781&oldid=843473014 Another Janagewen IP sock.

It's going away. There is no reference for industry-wide "generation" numbers. Jeh (talk) 19:32, 19 July 2018 (UTC)

Fixed: Large number of problems in the chronology table

Hello.

I fixed a large number of problems in the Chronology section. Here is a detailed list of what has gotten fixed:

• Erroneous info: IA-64 and ARM64 were framed into the chronology, in a way that implied they were implementations of x86! And that's the smallest problem; this integration was so weird, it was analogous to reading an article on the life of Bill Gates that frequently strayed off the topic to explain the details of Beyonce's life in parallel. Whatever the noble motive of the original writer, the end result grossly failed to justify itself.
• Writer's pet peeves: Apparently the writer had felt the need to emphatically explain that "x64" is part of "x86". But the irony is this act would backfire because the integration of erroneous info about IA-64 and ARM64. It is like the story of the boy called wolf for the third time; when you (by mistake or intentionally) tell people that IA-64 and ARM64 are part of x86, and they find out otherwise, they don't believe you when you tell them x64 is an x86 version.
• Ambiguous info: Intel Core i3, i5 and i7 are CPU brand names, not CPU models; these brand names have been used since 2008 for the bulk of Intel products. I replaced them with the Intel CPU architecture names, e.g., Nehalem.
• Conflicting top and bottom headings:
  • "Generation" ≠ "Era" (one is time, one is the product of it)
  • "Introduction" ≠ "Release" (one happens once, the other can happen repeatedly afterwards)
  • "Prominent CPU models" ≠ "CPU models" (not every CPU is prominent)
  • "Address Space" ≠ "Physical Address Space", especially when right below the former, it says "Physical", "virtual" and "linear"
  • "Notable features" ≠ "New features" (one feature can be new but not notable)
• Contested info: Please read previous discussions in this talk page
• Editorializing (e.g. "Enhanced Platform", which is zero-informative. Proof: [1])
• Broken links
• Incorrect use of slash; see MOS:SLASH
• Capitalization; see MOS:CAPS
• "NA" → "{{N/A}}"

5.78.104.231 (talk) 08:35, 28 August 2018 (UTC)

@5.78.104.231: I've no comments about your words, but would you please design or devise completely a new table rather than modifying mine? 221.9.14.156 (talk) 23:32, 4 September 2018 (UTC)

You (221.9.14.156) are quite obviously the long-permanent-blocked Janagewen (see user:Janagewen, WP:Sockpuppet_investigations/Janagewen/Archive, etc.). You are permanently blocked from editing due to a wide variety of problems, as detailed at your various case pages. I have therefore reverted your change and will continue to do so. Jeh (talk) 00:51, 5 September 2018 (UTC)

Two "Overview" sections

The first and fourth sections of this article are both named "Overview". The first one provides some background information and description of modern implementation mostly in layman's terms, while the other goes into technical details.

I Require The Table in the Main Article to Be Removed!

It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement! --- Aaron Janagewen — Preceding unsigned comment added by 221.9.17.84 (talk) 22:08, 1 October 2018 (UTC)

Semi-protected edit request on 1 October 2018

It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement! --- Aaron Janagewen 221.9.17.84 (talk) 22:11, 1 October 2018 (UTC)

 Not done: please establish a consensus for this alteration before using the {{edit semi-protected}} template. RudolfRed (talk) 22:48, 1 October 2018 (UTC)

I require the table on the section Chronology getting back to its previous version, as below

First introduced	Prominent CPU brands	Linear address size (bits)	Segment / offset size (bits)	Physical address size (bits)	Notable (new) features
1978	Intel 8086, Intel 8088 and clones	16	—	20	First x86 microprocessors
1982	Intel 80186, Intel 80188 and clones, NEC V20/V30	16	—	20	Hardware for fast address calculations, fast multiplication and division
1982	Intel 80286 and clones	16	14 / 16	24	MMU, for protected mode and a larger address space
1985	Intel 80386 and clones, AMD Am386	32	14 / 32	32	32-bit instruction set, MMU with paging, PGA132 socket
1989	Intel 80486 and clones, AMD Am486	32	14 / 32	32	RISC-like pipelining, integrated x87 FPU (80-bit), on-chip cache, PGA168 socket
1992	Cyrix Cx486SLC, Cyrix Cx486DLC	32	14 / 32	32	L1 cache and pipelining introduced into the 386 platform, PGA132 socket
1993	Pentium, Pentium MMX, Rise mP6	32	14 / 32	32	Superscalar, 64-bit databus, faster FPU, MMX (2× 32-bit), Socket 7, SMP
1995	Pentium Pro	32	14 / 32	36 (PAE)	µ-op translation, conditional move instructions, out-of-order, register renaming, speculative execution, PAE (Pentium Pro), in-package L2 cache (Pentium Pro), Socket 8
1996	AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III-Samuel (2000), VIA C3-Samuel2 / VIA C3-Ezra (2001)	32	14 / 32	32	Discrete microarchitecture (µ-op translation)
1997	Am5x86, Cyrix 5x86, Pentium OverDrive	32	14 / 32	32	Partial Pentium's specification brought into the 486 platform
1997	Pentium II/III, Celeron, Xeon	32	14 / 32	36 (PAE)	SSE (2× 64-bit), on-die L2 Cache (Mendocino, Coppermine), SLOT 1 or Socket 370
1997	AMD K6/2/III, Cyrix III-Joshua (2000)	32	14 / 32	32	On-die L2-Cache (K6-III, Cyrix III Joshua), 3DNow!, no PAE support, Super Socket 7 (K6-2)
1999	Athlon, Athlon XP	32	14 / 32	36 (PAE)	Superscalar FPU, wide design (up to three x86 instr./clock), Slot A or Socket A, SMP
2000	Pentium 4	32	14 / 32	36 (PAE)	Deeply pipelined, 20 pipeline stages, Intel VT-x, Rapid Execution Engine, Execution Trace Cache, Replay system, Quad-Pumped Front-Side Bus, high frequency, SSE2, hyper-threading, Socket 478
2000	Transmeta Crusoe, Transmeta Efficeon	32	14 / 32	32	VLIW design with x86 emulator, on-die memory controller
2001	Intel Itanium IA-32 compatibility mode	32	14 / 32	N/A	EPIC architecture with an on-package engine (pre-2006 chips, later using IA-32 Execution Layer) that provides backward support for most IA-32 applications
2003	Pentium M, VIA C7 (2005), Intel Core (2006)	32	14 / 32	36 (PAE)	Optimized for low thermal design power, four pumped FSB, μ-op fusion
2003	Athlon 64, Athlon 64 X2 (2005), Sempron (2004), Opteron	64	—	36 (Athlon FX, Sampron)/40 (Opteron)	AMD64 processor (excluding 32-bit Sempron), on-die memory controller, HyperTransport, CMP, virtualization (AMD-V) on some models, Socket 754/939/940 or AM2 socket
2005	Pentium 4 Prescott F/506/516/5x1/6xx, Celeron D 3x1/3x6/355, Pentium D	64	—	36	EM64T technology introduced, very deeply pipelined, 31 pipeline stages, high frequency, SSE3, LGA 775 socket, CMP, x86-64
2006	Intel Core 2	64	—	36 (Intel Core 2, Xeon 5100 /40 (Xeon 7200/7300 on LGA771)	Intel 64 processor, low power, multi-core, lower clock frequency, SSE4 (Penryn), wide dynamic execution, µ-op fusion, macro-µ-op fusion, virtualization (Intel VT) on some models
2007	DM&P Vortex86	32	14 / 32	36	in-order core with high pipeline, deep integrated with sound&graphic unit(SoC), on-chip memory controller, low clock, low power for embedded use
2007	AMD Phenom, AMD Phenom II (2008)	64	—	40 (Phenom, Athlon, Sampron)/48 (Phenom II, Opteron)	Monolithic quad-core, SSE4a, HyperTransport 3, AM2+ or AM3 socket
2008	VIA Nano	64	—	36	Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption; very low power; adaptive power management
2008	1st gen. Intel Core i3, i5 and i7 (Nehalem and Westmere)	64	—	40	Hyper-Threading, Intel Turbo Boost 1.0, AES-NI, Out-of-order, QuickPath, native memory controller, on-die L3 cache, modular, Intel HD Graphics introduced onto CPU chip (Clarkdale), LGA 1366 (Nehalem) or LGA 1156 socket
2008	Intel Atom	32	14 / 32	32 (Bonnell) 36 (Bay Trailer and later)	In-order but highly pipelined, very-low-power, some models (Diamondville) with 32-bit (integer CPU), on-die GPU (Penwell, Cedarview)
2010	AMD FX	64	—	48 (FX) 52(Opteron)	highly pipelined, about 20 stages long pipeline, very-power hungry, very high clock, share instruction cache and FlexFPU between two cores in the module, first consumer octa-core processor, CMT (Clustered Multi-Thread), FMA, OpenCL, support up to 64 socket per chipset.
2011	AMD APU C, E and Z Series (Bobcat)	64	—	36	Out-of-order, 64-bit (integer CPU), on-die GPU; low power (Bobcat), Socket FM1 (Desktop)
2011	AMD APU A and E Series (Llano)	64	—	40	on-die GPU, first generation fusion APU
2011	AMD APU A Series (Bulldozer, Trinity and later)	64	—	48	SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU, Socket FM2 or Socket FM2+, GPGPU
2011	2nd and 3rd gen. Intel Core i3, i5 and i7 (Sandy Bridge and Ivy Bridge)	64	—	42	Internal Ring connection, Intel Turbo Boost 2.0, F16C AVX, GPGPU, Micro-operation cache(Uop Cache), relatively long pipeline (14 to 19 stages),LGA 1155 socket.
2012	Intel Xeon Phi (Larrabee)	64	—	36	many integrated core (MIC) architecture (w/62), in-order P54C with x86-64, very wide vector unit, LRBni instructions (8× 64-bit), four threads per core.
2013	4th and 5th gen. Intel Core i3, Core i5 and Core i7 (Haswell and Broadwell)	64	—	44	AVX2, FMA3, TSX, BMI1, BMI2 and ABM instructions, Intel ADX, Fully integrated voltage regulator (FIVR), Intel Turbo Boost 3.0 Max(Broadwell-E), high clock rate, LGA 1150 or LGA 2011 socket
2015	6th, 7th and 8th gen. Intel Core i3, i5, i7 and i9 (Skylake, Kaby Lake and Coffee Lake)	64	—	46	Out-of-order, 64-bit (integer CPU), AVX-512, Intel SGX, Intel MPX, high clock rate, integrated on-die southbridge, integrated on-die x86 MIC array GPU, SoC, MIC, LGA 1151 socket.
2017	AMD Ryzen 3, Ryzen 5, Ryzen 7 and Ryzen Threadripper (Zen and Zen+)	64	—	48	Multiple CCXs connected through infinity Fabric, eXtended Frequency Range (XFR), SenseMI, Simultaneous Multi Threading (SMT), AM4/TR4 Socket
First introduced	Prominent CPU brands	Linear address size (bits)	Segment / offset size (bits)	Physical address size (bits)	Notable (new) features

Semi-protected edit request on 2 October 2018

- ! First introduced ! Prominent CPU brands ! Linear address size (bits) ! Segment / offset size (bits) ! Physical address size (bits) ! Notable (new) features 221.9.17.84 (talk) 00:42, 2 October 2018 (UTC)