Epyc

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AMD Epyc
AMD Epyc wordmark.svg
General information
LaunchedJune 2017
Marketed byAMD
Designed byAMD
Common manufacturer(s)
Performance
Max. CPU clock rate2.7 GHz to 4.1 GHz
Architecture and classification
Technology node14 nm to 7 nm
MicroarchitectureZen
Zen 2
Zen 3
Zen 4
Instruction setx86-64
MMX(+), SSE1, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, AVX2, FMA3, CVT16/F16C, ABM, BMI1, BMI2
AES, CLMUL, RDRAND, SHA, SME
AMD-V, AMD-Vi
Physical specifications
Cores
  • up to 128 cores/256 threads on dual-socket systems
Socket(s)
Products, models, variants
Core name(s)
  • Naples
  • Rome
  • Milan
  • Genoa
  • Bergamo
Brand name(s)
  • Epyc
History
PredecessorOpteron

EPYC is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.[1] Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using Infinity Fabric interchip interconnect.

History[edit]

In March 2017, AMD announced a server platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May.[2] That June, AMD officially launched Epyc by releasing the Epyc 7001 series processors.[3] Two years later, in August 2019, the Epyc 7002 series processors based on the Zen 2 microarchitecture released, bringing much better performance and double the cores compared to their predecessors.

The Zen 3 based Epyc microarchitecture is codenamed "Milan".[4]

AMD EPYC CPU Codenames[5]
Gen Year Name Cores
1st 2017 Naples 32 × Zen 1
2nd 2019 Rome 64 × Zen 2
3rd 2021 Milan 64 × Zen 3
4th 2022 Genoa 96 × Zen 4
2023 Bergamo 128 × Zen 4c

Design[edit]

The platform includes one- and two-socket systems. In multi-processor configurations, two Epyc CPUs communicate via AMD's Infinity Fabric.[6] Each server chip supports 8 channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes from each are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.[7] All first generation Epyc processors are composed of four eight-core Zeppelin dies (the same die as found in Ryzen processors) in a multi-chip module, with the varying product core counts produced by symmetrically disabling cores of each core complex on each Zeppelin die.[8][9]

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some unavailable features require additional controller chips to make them available on the system.

The first generation of Epyc microprocessors were manufactured by GlobalFoundries using a 14 nm FinFET process licensed from Samsung Electronics.[10] Epyc 2 will be manufactured by TSMC using a 7 nm FinFET process.[11]

Reception[edit]

Initial reception to Epyc was generally positive.[12] Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.[12] In 2021, Meta Platforms selected Epyc chips for its metaverse data centers.[13]

Features[edit]

CPU features table

Products[edit]

Server[edit]

First generation Epyc (Naples)[edit]

The following table lists the devices using the first generation design.

A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCI-E lanes from each processor for the communication between processors.

Model Release date
and price
Fab Chiplets Cores
(threads)
Core Config[i] Clock rate (GHz) Cache Socket &
configuration
PCIe
Lanes
Memory
support
TDP
Base Boost L1 L2 L3
All-core Max
EPYC 7351P[14] [15][16] June 2017[17]
US $750
14 nm 4 × CCD 16 (32) 8 × 2 2.4 2.9 64 KB inst.
32 KB data
per core
512 KB
per core
64 MB
8 MB per CCX
SP3
1P
128 DDR4-2666
8 channels
155/170 W
EPYC 7401P[14] [15][16] June 2017[17]
US $1075
24 (48) 8 × 3 2.0 2.8 3.0
EPYC 7551P[14][15][16] June 2017[17]
US $2100
32 (64) 8 × 4 2.55 180 W
EPYC 7251[14][15][16] June 2017[17]
US $475
8 (16) 8 × 1 2.1 2.9 32 MB
4 MB per CCX
SP3
2P
DDR4-2400
8 channels
120 W
EPYC 7261[18] Mid 2018
US $700+
2.5 64 MB
8 MB per CCX
DDR4-2666
8 channels
155/170 W
EPYC 7281[14][15][16] June 2017[17]
US $650
16 (32) 8 × 2 2.1 2.7 32 MB
4 MB per CCX
EPYC 7301[14][15][16] June 2017[17]
US $800+
2.2 64 MB
8 MB per CCX
EPYC 7351[14][15][16] June 2017[17]
US $1100+
2.4 2.9 2.9
EPYC 7371[19] Late 2018
US $1550+
3.1 3.6 3.8 180 W
EPYC 7401[14][15][16] June 2017[17]
US $1850
24 (48) 8 × 3 2.0 2.8 3.0 155/170 W
EPYC 7451[14][15][16] June 2017[17]
US $2400+
2.3 2.9 3.2 180 W
EPYC 7501[14][15][16] June 2017[17]
US $3400
32 (64) 8 × 4 2.0 2.6 3.0 155/170 W
EPYC 7551[14][15][16] June 2017[17]
US $3400+
2.55 180 W
EPYC 7571 Late 2018
N/A
2.2 ? 200 W?
EPYC 7601[14][15][16] June 2017[17]
US $4200
2.7 3.2 180 W
  1. ^ Core Complexes (CCX) × cores per CCX


Second generation Epyc (Rome)[edit]

First generation Epyc processor

In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture.[20] The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip providing 128 PCIe lanes in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket.[21] The 7 nm "Rome" is manufactured by TSMC.[11] It was released on August 7, 2019.[22]

Common features of these CPUs:

  • Codenamed "Rome"
  • The number of PCI-E lanes: 128
  • Release date: August 7, 2019 except EPYC 7H12 which was released on September 18, 2019
  • Memory support: eight-channel DDR4-3200
Model Price Fab Chiplets Cores
(threads)
Core config[i] Clock rate (GHz) Cache Socket &
configuration
TDP
Base Boost L1 L2 L3
All-core Max
EPYC 7232P US $450 7 nm 2 × CCD
1 × I/O
8 (16) 4 × 2 3.1 3.2 32 KB inst.
32 KB data
per core
512 KB
per core
32 MB
8 MB per CCX
SP3
1P
120 W
EPYC 7302P US $825 4 × CCD
1 × I/O
16 (32) 8 × 2 3 3.3 128 MB
16 MB per CCX
155 W
EPYC 7402P US $1250 24 (48) 8 × 3 2.8 3.35 180 W
EPYC 7502P US $2300 32 (64) 8 × 4 2.5 3.35
EPYC 7702P US $4425 8 × CCD
1 × I/O
64 (128) 16 × 4 2 3.35 256 MB
16 MB per CCX
200 W
EPYC 7252 US $475 2 × CCD
1 × I/O
8 (16) 4 × 2 3.1 3.2 64 MB
16 MB per CCX
SP3
2P
120 W
EPYC 7262 US $575 4 × CCD
1 × I/O
8 × 1 3.2 3.4 128 MB
16 MB per CCX
155 W
EPYC 7272 US $625 2 × CCD
1 × I/O
12 (24) 4 × 3 2.9 3.2 64 MB
16 MB per CCX
120 W
EPYC 7282 US $650 16 (32) 4 × 4 2.8 3.2
EPYC 7302 US $978 4 × CCD
1 × I/O
8 × 2 3 3.3 128 MB
16 MB per CCX
155 W
EPYC 7352 US $1350 24 (48) 8 × 3 2.3 3.2
EPYC 7402 US $1783 8 × 3 2.8 3.35 180 W
EPYC 7452 US $2025 32 (64) 8 × 4 2.35 3.35 155 W
EPYC 7502 US $2600 8 × 4 2.5 3.35 180 W
EPYC 7532 US $3350 8 × CCD
1 × I/O
16 × 2 2.4 3.3 256 MB
16 MB per CCX
200 W
EPYC 7542 US $3400 4 × CCD
1 × I/O
8 × 4 2.9 3.4 128 MB
16 MB per CCX
225 W
EPYC 7552 US $4025 6 × CCD
1 × I/O
48 (96) 12 × 4 2.2 3.3 192 MB
16 MB per CCX
200 W
EPYC 7642 US $4775 8 × CCD
1 × I/O
16 × 3 2.3 3.3 256 MB
16 MB per CCX
225 W
EPYC 7662 US $6150 64 (128) 16 × 4 2 3.3 225 W
EPYC 7702 US $6450 2 3.35 200 W
EPYC 7742 US $6950 2.25 3.4 225 W
EPYC 7H12 2.6 3.3 280 W
EPYC 7F32 US $2100 4 × CCD
1 × I/O
8 (16) 8 × 1 3.7 3.9 128 MB
16 MB per CCX
SP3
1P/2P
180 W
EPYC 7F52 US $3100 8 × CCD
1 × I/O
16 (32) 16 × 1 3.5 3.9 256 MB
16 MB per CCX
240 W
EPYC 7F72 US $2450 6 × CCD
1 × I/O
24 (48) 12 × 2 3.2 3.7 192 MB
16 MB per CCX
240 W
  1. ^ Core Complexes (CCX) × cores per CCX


Third generation Epyc (Milan)[edit]

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture.[23] Milan chips will use Socket SP3, with up to 64 cores on package, and support eight channel DDR4 SDRAM and 128 PCIe 4.0 lanes.[23] It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.[23]

Milan CPUs were launched by AMD on 15 March 2021.[24]

Milan-X CPUs used in the upcoming Frontier exascale supercomputer are announced to add stacked 3D V-Cache chiplets to increase the maximum L3 cache capacity from 256 MB to 768 MB.[25]


Model Price Fab Chiplets Cores
(threads)
Core config[i] Clock rate (GHz) Cache Socket &
configuration
TDP
Base Boost L1 L2 L3
EPYC 7763 US $7890 7 nm 8 × CCD
1 × I/O
64 (128) 8 × 8 2.45 3.50 32 KB inst.
32 KB data
per core
512 KB
per core
256 MB
32 MB per CCX
SP3
2P
280 W
EPYC 7713 US $7060 2.00 3.675 225 W
EPYC 7713P US $5010 SP3
1P
EPYC 7663 US $6366 56 (112) 8 × 7 2.00 3.50 SP3
2P
240 W
EPYC 7643 US $4995 48 (96) 8 × 6 2.30 3.60 225 W
EPYC 75F3 US $4860 32 (64) 8 × 4 2.95 4.00 280 W
EPYC 7543 US $3761 2.80 3.70 225 W
EPYC 7543P US $2730 SP3
1P
EPYC 7513 US $2840 2.60 3.65 128 MB
16 MB per CCX
SP3
2P
200 W
EPYC 7453 US $1570 4 × CCD
1 × I/O
28 (56) 4 × 7 2.75 3.45 64 MB
16 MB per CCX
225 W
EPYC 74F3 US $2900 8 × CCD
1 × I/O
24 (48) 8 × 3 3.20 4.00 256 MB
32 MB per CCX
240 W
EPYC 7443 US $2010 4 × CCD
1 × I/O
4 × 6 2.85 4.00 128 MB
32 MB per CCX
200 W
EPYC 7443P US $1337 SP3
1P
EPYC 7413 US $1825 2.65 3.60 SP3
2P
180 W
EPYC 73F3 US $3521 8 × CCD
1 × I/O
16 (32) 8 × 2 3.50 4.00 256 MB
32 MB per CCX
240 W
EPYC 7343 US $1565 4 × CCD
1 × I/O
4 × 4 3.20 3.90 128 MB
32 MB per CCX
190 W
EPYC 7313 US $1083 3.00 3.70 155 W
EPYC 7313P US $913 SP3
1P
EPYC 72F3 US $2468 8 × CCD
1 × I/O
8 (16) 8 × 1 3.70 4.10 256 MB
32 MB per CCX
SP3
2P
180 W
  1. ^ Core Complexes (CCX) × cores per CCX


Embedded[edit]

First generation Epyc (Snowy Owl)[edit]

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.[26]


Model Release
date
Fab Chiplets Cores
(threads)
Core Config[i] Clock rate (GHz) Cache Socket PCIe
lanes
Ethernet Memory
support
TDP Junction temperature (°C)
Base Boost L1 L2 L3
All-core Max
EPYC 3101 February 2018 14 nm 1 x CCD 4 (4) 1 × 4 2.1 2.9 2.9 64 KB inst.
32 KB data
per core
512 KB
per core
8 MB SP4r2 32 4 × 10GbE DDR4-2666
dual-channel
35 W 0-95
EPYC 3151 4 (8) 2 × 2 2.7 2.9 2.9 16 MB
8 MB per CCX
45 W
EPYC 3201 8 (8) 2 × 4 1.5 3.1 3.1 DDR4-2133
dual-channel
30 W
EPYC 3251 8 (16) 2.5 3.1 3.1 DDR4-2666
dual-channel
55 W 0-105
EPYC 3255 Un­known 25-55 W -40-105
EPYC 3301 February 2018 2 x CCD 12 (12) 4 × 3 2.0 2.15 3.0 32 MB
8 MB per CCX
64 8 × 10GbE DDR4-2666
quad-channel
65 W 0-95
EPYC 3351 12 (24) 1.9 2.75 3.0 SP4 60-80 W 0-105
EPYC 3401 16 (16) 4 × 4 1.85 2.25 3.0 SP4r2 85 W
EPYC 3451 16 (32) 2.15 2.45 3.0 SP4 80-100 W
  1. ^ Core Complexes (CCX) × cores per CCX


Chinese variants[edit]

A variant created for the Chinese server market by an AMD–Chinese joint venture is the Hygon Dhyana system on a chip.[27][28] It is noted to be a variant of the AMD EPYC, and is so similar that "there is little to no differentiation between the chips".[27] It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".[28] Later Benchmarks showed that certain floating point instructions are performing worse and AES is disabled, probably to comply with US export restrictions.[29] Cryptography extensions are replaced by Chinese variants.[30]

References[edit]

  1. ^ Cutress, Ian. "Computex 2017: AMD Press Event Live Blog". www.anandtech.com.
  2. ^ Kampman, Jeff (16 May 2017). "AMD's Naples datacenter CPUs will make an Epyc splash". Tech Report. Retrieved 16 May 2017.
  3. ^ Cutress, Ian (20 June 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". Anandtech.com. Retrieved 12 July 2017.
  4. ^ Cutress, Ian (2019-06-24). "An Interview with AMD's Forrest Norrod: Naples, Rome, Milan, & Genoa". AnandTech.com.
  5. ^ Cutress, Ian (2019-05-27). "AMD Confirms Zen 4 EPYC Codename, and Elaborates on Frontier Supercomputer CPU". AnandTech.com.
  6. ^ Kampman, Jeff (7 March 2017). "AMD's Naples platform prepares to take Zen into the datacenter". Tech Report. Retrieved 7 March 2017.
  7. ^ Cutress, Ian (7 March 2017). "AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2". Anandtech. Retrieved 7 March 2017.
  8. ^ Shrout, Ryan (20 June 2017). "AMD EPYC 7000 Series Data Center Processor Launch – Gunning for Xeon | Architectural Outlook". www.pcper.com. Retrieved 9 August 2019.
  9. ^ Morgan, Timothy Prickett (May 17, 2017). "AMD Disrupts The Two-Socket Server Status Quo". www.nextplatform.com.
  10. ^ Morris, John (March 13, 2018). "Inside GlobalFoundries' long road to the leading edge". ZDNet. Retrieved 17 July 2019.
  11. ^ a b Smith, Ryan (July 26, 2018). "AMD "Rome" EPYC CPUs to Be Fabbed By TSMC". AnandTech. Retrieved 18 June 2019.
  12. ^ a b De Gelas, Johan; Cutress, Ian (11 July 2017). "Sizing Up the Servers: Intel's Skylake-SP Xeon vs AMD's EPYC 7000". Anandtech. Retrieved 11 July 2017.
  13. ^ Sozzi, Brian (2021-11-08). "Chipmaker AMD just scored a big deal with Meta". finance.yahoo.com.
  14. ^ a b c d e f g h i j k l "AMD EPYC 7000 Series Processors: Leading Performance for the Cloud Era" (PDF). Advanced Micro Devices, Inc. August 2018. p. 2.
  15. ^ a b c d e f g h i j k l Cutress, Ian (20 June 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". Anand Tech. Retrieved 21 June 2017.
  16. ^ a b c d e f g h i j k l Cutress, Ian (20 June 2017). "AMD EPYC Launch Event Live Blog". Anand Tech. Retrieved 21 June 2017.
  17. ^ a b c d e f g h i j k l Kennedy, Patrick (16 May 2017). "AMD EPYC New Details on the Emerging Server Platform". Serve The Home. Retrieved 16 May 2017.
  18. ^ "AMD EPYC 7261 | AMD". www.amd.com. Retrieved 2019-01-20.
  19. ^ "AMD PS7371BEVGPAF EPYC 7371 3.1GHz 16-Core". www.gamepc.com. Retrieved 2019-01-20.
  20. ^ "AMD Takes High-Performance Datacenter Computing to the Next Horizon". AMD. Retrieved 2018-12-06.
  21. ^ Gordon Mah Ung (2018-11-07). "What AMD's 64-core 'Rome' server CPU tells us about Ryzen 2". PCWorld. Retrieved 2018-11-08.
  22. ^ "2nd Gen AMD EPYC Processors Set New Standard for the Modern Datacenter with Record-Breaking Performance and Significant TCO Savings". AMD. August 7, 2019. Retrieved August 8, 2019.
  23. ^ a b c Alcorn, Paul (5 October 2019). "AMD dishes on Zen 3 and Zen 4 architecture, Milan and Genoa roadmap". Tom's Hardware. Retrieved 5 October 2019.
  24. ^ Trader, Tiffany (2021-03-15). "AMD Launches Epyc 'Milan' with 19 SKUs for HPC, Enterprise and Hyperscale". HPCwire.
  25. ^ "AMDs Exascale-Hammer: Epyc 3 mit 804 MByte Cache, Instinct MI200 mit 47,9 TFlops". c't Magazin (in German). 2021-11-08.
  26. ^ Alcorn, Paul (21 February 2018). "AMD Launches Ryzen Embedded V1000, EPYC Embedded 3000 Processors". tom's HARDWARE. Retrieved 5 April 2018.
  27. ^ a b Alcorn, Paul (6 July 2018). "China Finds Zen: Begins Production Of x86 Processors Based On AMD's IP". Tom's Hardware. Retrieved 9 July 2018.
  28. ^ a b Larabel, Michael (9 June 2018). "Hygon Dhyana: Chinese x86 Server CPUs Based On AMD Zen". Phoronix. Retrieved 9 July 2018.
  29. ^ Cutress, Ian. "Testing a Chinese x86 CPU: A Deep Dive into Zen-based Hygon Dhyana Processors". www.anandtech.com.
  30. ^ Cutress, Ian, & Wilson, Wendell. "Testing a Chinese x86 CPU: A Deep Dive into Zen-based Hygon Dhyana Processors". www.anandtech.com. Retrieved 2020-09-29.