- Not to be confused with x86-64, the 64-bit extension to x86 architecture.
|Designer||HP and Intel|
|General purpose||128; 64 1-bit predicate registers|
IA-64 (also called Intel Itanium architecture) is the architecture of the Itanium family of 64-bit Intel microprocessors. The architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel.
The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with other superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle. The first Itanium processor, codenamed Merced, was released in 2001.
- 1 History
- 2 Architecture
- 3 Hardware support
- 4 Software support
- 5 Competition
- 6 Supercomputers and high-performance computing
- 7 Processors
- 8 Market reception
- 9 See also
- 10 References
- 11 External links
In 1989, HP determined that reduced instruction set computing (RISC) architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture, later named explicitly parallel instruction computing (EPIC), that allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, in which a single instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel. The goal of this approach is twofold: to enable deeper inspection of the code at compile time to identify additional opportunities for parallel execution, and to simplify processor design and reduce energy consumption by eliminating the need for runtime scheduling circuitry.
HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.
During development, Intel, HP, and industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computing (CISC) architectures for all general-purpose applications. Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures respectively in favor of migrating to IA-64.
Several groups developed operating systems for the architecture, including Microsoft Windows, Linux, and UNIX variants such as HP-UX, Solaris, Tru64 UNIX, and Monterey/64 (the last three were canceled before reaching the market). By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of Merced began slipping. Technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches. There were also structural problems within the project, as the two parts of the joint team used different methodologies and had slightly different priorities. Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more research was needed.
Intel announced the official name of the processor, Itanium, on October 4, 1999. Within hours, the name Itanic had been coined on a Usenet newsgroup, a reference to Titanic, the "unsinkable" ocean liner that sank in 1912.
Itanium (Merced): 2001
|Produced||From June 2001 to June 2002|
|Max. CPU clock rate||733 MHz to 800 MHz|
|FSB speeds||266 MT/s|
|L2 cache||96 KB|
|L3 cache||2 or 4 MB|
By the time Itanium was released in June 2001, its performance was not superior to competing RISC and CISC processors.
Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to market a year later.
Itanium 2: 2002–2010
Itanium 2 processor
|Produced||From 2002 to 2010|
|Max. CPU clock rate||900 MHz to 2.53 GHz|
|Cores||1, 2, 4 or 8|
|L2 cache||256 KB on Itanium2
256 KB (D) + 1 MB(I) or 512 KB (I) on (Itanium2 9x00 series)
|L3 cache||1.5-32 MB|
The Itanium 2 processor was released in 2002. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem.
In 2003, AMD released the Opteron, which implemented its own 64-bit architecture (x86-64). Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from x86. Intel responded by implementing x86-64 in its Xeon microprocessors in 2004.
In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate software porting.
In 2006, Intel delivered Montecito (marketed as the Itanium 2 9000 series), a dual-core processor that roughly doubled performance and decreased energy consumption by about 20 percent.
Itanium 9300 (Tukwila): 2010
The device uses a 65 nm process, includes two to four cores, up to 24 MB on-die caches, Hyper-Threading technology and integrated memory controllers. It implements double-device data correction (DDDC), which helps to fix memory errors. Tukwila also implements Intel QuickPath Interconnect (QPI) to replace the Itanium bus-based architecture. It has a peak interprocessor bandwidth of 96 GB/s and a peak memory bandwidth of 34 GB/s. With QuickPath, the processor has integrated memory controllers and interfaces the memory directly, using QPI interfaces to directly connect to other processors and I/O hubs. QuickPath is also used on Intel processors using the Nehalem microarchitecture, making it probable that Tukwila and Nehalem will be able to use the same chipsets. Tukwila incorporates four memory controllers, each of which supports multiple DDR3 DIMMs via a separate memory controller, much like the Nehalem-based Xeon processor code-named Beckton.
Itanium 9500 (Poulson): 2012
The Itanium 9500 series processor, codenamed Poulson, is the follow-on processor to Tukwila features eight cores, has a 12-wide issue architecture, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization. The Poulson L3 cache size is 32 MB. L2 cache size is 6 MB, 512 I KB, 256 D KB per core. Die size is 544 mm², less than its predecessor Tukwila (698.75 mm²).
At ISSCC 2011, Intel presented a paper called, "A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium Processor for Mission Critical Servers." Given Intel's history of disclosing details about Itanium microprocessors at ISSCC, this paper most likely refers to Poulson. Analyst David Kanter speculates that Poulson will use a new microarchitecture, with a more advanced form of multi-threading that uses as many as two threads, to improve performance for single threaded and multi-threaded workloads. Some new information was released at Hotchips conference. New information presents improvements in multithreading, resiliency improvements (Instruction Replay RAS) and few new instructions (thread priority, integer instruction, cache prefetching, data access hints).
Intel has extensively documented the Itanium instruction set and microarchitecture, and the technical press has provided overviews. The architecture has been renamed several times during its history. HP originally called it PA-WideWord. Intel later called it IA-64, then Itanium Processor Architecture (IPA), before settling on Intel Itanium Architecture, but it is still widely referred to as IA-64.
It is a 64-bit register-rich explicitly parallel architecture. The base data word is 64 bits, byte-addressable. The logical address space is 264 bytes. The architecture implements predication, speculation, and branch prediction. It uses a hardware register renaming mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.
The architecture implements 128 integer registers, 128 floating point registers, 64 one-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results.
Each 128-bit instruction word contains three instructions, and the fetch mechanism can read up to two instruction words per clock from the L1 cache into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the instruction set, and each unit executes at a rate of one instruction per cycle unless execution stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units.
The execution unit groups include:
- Six general-purpose ALUs, two integer units, one shift unit
- Four data cache units
- Six multimedia units, two parallel shift units, one parallel multiply, one population count
- Two 82-bit floating-point multiply–accumulate units, two SIMD floating-point multiply–accumulate units (two 32-bit operations each)
- Three branch units
The compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a multiply–accumulate operation, a single floating point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four FLOPs per cycle. For example, the 800 MHz Itanium had a theoretical rating of 3.2 GFLOPS and the fastest Itanium 2, at 1.67 GHz, was rated at 6.67 GFLOPS.
From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KB. The Level 3 cache was also unified and varied in size from 1.5 MB to 24 MB. The 256 KB L2 cache contains sufficient logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU).
Main memory is accessed through a bus to an off-chip chipset. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2×128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/s, and the 533 MHz Montecito bus transfers 17.056 GB/s
Itanium processors released prior to 2006 had hardware support for the IA-32 architecture to permit support for legacy server applications, but performance for IA-32 code was much worse than for native code and also worse than the performance of contemporaneous x86 processors. In 2005, Intel developed the IA-32 Execution Layer (IA-32 EL), a software emulator that provides better performance. With Montecito, Intel therefore eliminated hardware support for IA-32 code.
- Hardware multithreading: Each processor core maintains context for two threads of execution. When one thread stalls during memory access, the other thread can execute. Intel calls this "coarse multithreading" to distinguish it from the "hyper-threading technology" Intel integrated into some x86 and x86-64 microprocessors.
- Hardware support for virtualization: Intel added Intel Virtualization Technology (Intel VT-i), which provides hardware assists for core virtualization functions. Virtualization allows a software "hypervisor" to run multiple operating system instances on the processor concurrently.
- Cache enhancements: Montecito added a split L2 cache, which included a dedicated 1 MB L2 cache for instructions. The original 256 KB L2 cache was converted to a dedicated data cache. Montecito also included up to 12 MB of on-die L3 cache.
The Itanium bus interfaces to the rest of the system via a chipset. Enterprise server manufacturers differentiate their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers. The chipset is the heart of the system-level architecture for each system design. Development of a chipset costs tens of millions of dollars and represents a major commitment to the use of the Itanium. IBM created a chipset in 2003, and Intel in 2002, but neither of them has developed chipsets to support newer technologies such as DDR2 or PCI Express. Currently, modern chipsets for Itanium supporting such technologies are manufactured by HP, Fujitsu, SGI, NEC, and Hitachi.
The "Tukwila" Itanium processor model had been designed to share a common chipset with the Intel Xeon processor EX (Intel’s Xeon processor designed for four processor and larger servers). The goal is to streamline system development and reduce costs for server OEMs, many of whom develop both Itanium- and Xeon-based servers. However, in 2013 this goal was pushed back to "evaluated for future implementation opportunities".
By now, only a few operating system support it.
To allow more software to run on the Itanium, Intel supported the development of compilers optimized for the platform, especially its own suite of compilers. Starting in November 2010, with the introduction of new product suites, the Intel Itanium Compilers were no longer bundled with the Intel x86 compilers in a single product. Intel offers Itanium tools and Intel x86 tools, including compilers, independently in different product bundles. GCC, Open64 and Microsoft Visual Studio 2005 (and later) are also able to produce machine code for Itanium. According to the Itanium Solutions Alliance over 13,000 applications were available for Itanium-based systems in early 2008, though Sun has contested Itanium application counts in the past. The ISA also supported Gelato, an Itanium HPC user group and developer community that ported and supported open source software for Itanium.
Emulation is a technique that allows a computer to execute binary code that was compiled for a different type of computer. Before IBM's acquisition of QuickTransit in 2009, application binary software for IRIX/MIPS and Solaris/SPARC could run via type of emulation called "dynamic binary translation" on Linux/Itanium. Similarly, HP implemented a method to execute PA-RISC/HP-UX on the Itanium/HP-UX via emulation, to simplify migration of its PA-RISC customers to the radically different Itanium instruction set. Itanium processors can also run the mainframe environment GCOS from Groupe Bull and several x86 operating systems via Instruction Set Simulators.
Itanium is aimed at the enterprise server and high-performance computing (HPC) markets. Other enterprise- and HPC-focused processor lines include Oracle Corporation's SPARC T5 and M5, Fujitsu's SPARC64 X and IBM's POWER7. Measured by quantity sold, Itanium's most serious competition comes from x86-64 processors including Intel's own Xeon line and AMD's Opteron line. As of 2009[update], most servers were being shipped with x86-64 processors.
In 2005, Itanium systems accounted for about 14% of HPC systems revenue, but the percentage has declined as the industry shifts to x86-64 clusters for this application.
An October 2008 paper, by Gartner on the Tukwila processor stated that "...the future roadmap for Itanium looks as strong as that of any RISC peer like Power or SPARC."
Supercomputers and high-performance computing
An Itanium-based computer first appeared on the list of the TOP500 supercomputers in November 2001. The best position ever achieved by an Itanium 2 based system in the list was #2 (while now all systems have dropped off the list), achieved in June 2004, when Thunder (LLNL) entered the list with an Rmax of 19.94 Teraflops. In November 2004, Columbia entered the list at #2 with 51.8 Teraflops, and there was at least one Itanium-based computer in the top 10 from then until June 2007. The peak number of Itanium-based machines on the list occurred in the November 2004 list, at 84 systems (16.8%); by June 2012, this had dropped to one system (0.2%), and no Itanium system remained on the list in November 2012.
The Itanium processors show a progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and front-side bus frequency of up to 667 MHz.
|Merced||180 nm||2001-06||733 MHz||96 KB||none||266 MHz||1||1||116||2 MB off-die L3 cache|
|800 MHz||130||4 MB off-die L3 cache|
|McKinley||180 nm||2002-07-08||900 MHz||256 KB||1.5 MB||400 MHz||1||1||130||HW branchlong|
|1 GHz||3 MB||130|
|Madison||130 nm||2003-06-30||1.3 GHz||3 MB||130|
|1.4 GHz||4 MB||130|
|1.5 GHz||6 MB||130|
|2003-09-08||1.4 GHz||1.5 MB||130|
|2004-04||1.4 GHz||3 MB||130|
|Deerfield||2003-09-08||1.0 GHz||1.5 MB||62||Low voltage|
|Hondo||2004-Q1||1.1 GHz||4 MB||400 MHz||2||1||260||32 MB L4|
|Fanwood||2004-11-08||1.6 GHz||3 MB||533 MHz||1||1||130|
|1.3 GHz||400 MHz||62?||Low voltage|
|Madison||2004-11-08||1.6 GHz||9 MB||400 MHz||130|
|2005-07-05||1.67 GHz||6 MB||667 MHz||130|
|2005-07-18||1.67 GHz||9 MB||667 MHz||130|
|Itanium 2 9000 series|
|Montecito||90 nm||2006-07-18||1.4 GHz||256 KB (D)+
1 MB (I)
|6–24 MB||400 MHz||1||2||104||Virtualization, Multithread, no HW IA-32|
|1.6 GHz||533 MHz|
|Itanium 2 9100 series|
|Montvale||90 nm||2007-10-31||1.42–1.66 GHz||256 KB (D)+
1 MB (I)
|8–24 MB||400–667 MHz||1||1–2||75–104||Core-level lockstep, demand-based switching|
|Itanium 9300 series|
|Tukwila||65 nm||2010-02-08||1.33-1.73 GHz||256 KB (D)+
512 KB (I)
|10–24 MB||QPI with a speed of 4.8 GT/s||1||2–4||130–185||A new point-to-point processor interconnect, the QPI, replacing the FSB. Turbo Boost|
|Itanium 9500 series|
|Poulson||32 nm||2012-11-08||1.73-2.53 GHz||256 KB (D)+
512 KB (I)
|20-32 MB||QPI with a speed of 6.4 GT/s||1||4-8||130–170||Doubled issue width (from 6 to 12 instructions per cycle), Instruction Replay technology, Dual-domain hyperthreading|
High-end server market
When first released in 2001, Itanium's performance, compared to better-established RISC and CISC processors, was disappointing. Emulation to run existing x86 applications and operating systems was particularly poor, with one benchmark in 2001 reporting that it was equivalent at best to a 100 MHz Pentium in this mode (1.1 GHz Pentiums were on the market at that time). Itanium failed to make significant inroads against IA-32 or RISC, and then suffered from the successful introduction of x86-64 based systems into the high-end server market, systems which were more compatible with the older x86 applications. Journalist John C. Dvorak, commenting in 2009 on the history of the Itanium processor, said "This continues to be one of the great fiascos of the last 50 years" in an article titled "How the Itanium Killed the Computer Industry". Tech columnist Ashlee Vance commented that the delays and underperformance "turned the product into a joke in the chip industry." In an interview, Donald Knuth said "The Itanium approach...was supposed to be so terrific—until it turned out that the wished-for compilers were basically impossible to write."
Both Red Hat and Microsoft announced plans to drop Itanium support in their operating systems due to lack of market interest; however, other Linux distributions such as Debian remain available for Itanium. On March 22, 2011, Oracle announced discontinuation of development on Itanium, although its technical support for its existing products would continue. On October 20, 2013, Oracle has officially written about its commitment to release Oracle Database 18.104.22.168.0 on HP-UX Itanium 11.31 by early 2014.
A former Intel official reported that the Itanium business had become profitable for Intel in late 2009. By 2009, the chip was almost entirely deployed on servers made by HP, which had over 95% of the Itanium server market share, making the main operating system for Itanium HP-UX. On March 22, 2011 Intel reaffirmed its commitment to Itanium with multiple generations of chips in development and on schedule.
Although Itanium did attain limited success in the niche market of high-end computing, Intel had originally hoped it would find broader acceptance as a replacement for the original x86 architecture.
AMD chose a different direction, designing the less radical x86-64, a 64-bit extension to the existing x86 architecture, which Microsoft then supported, forcing Intel to introduce the same extensions in its own x86-based processors. These designs can run existing 32-bit applications at native hardware speed, while offering support for 64-bit memory addressing and other enhancements to new applications. This architecture has now become the predominant 64-bit architecture in the desktop and portable market. Although some Itanium-based workstations were initially introduced by companies such as SGI, they are no longer available.
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