User:Honeydurga/IP, ARM, Xscale and PXA320
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- 1 Intellectual property
- 2 ARM Holdings
- 3 ARM cores
- 4 Architecture
- 5 Operating systems
Intellectual property (IP) refers to creations of the mind: inventions, literary and artistic works, and symbols, names, images, and designs used in commerce. IP is divided into two categories:
- Industrial property, which includes inventions (patents), trademarks, industrial designs, and geographic indications of source; and
- Copyright: which includes architectural designs.
ARM Holdings is the world's leading semiconductor intellectual property (IP) supplier. The ARM business model involves the designing and licensing of IP rather than the manufacturing and selling of actual semiconductor chips. They licence IP to a network of Partners, which includes the world's leading semiconductor and systems companies. These Partners utilize ARM IP designs to create and manufacture system-on-chip designs, paying ARM a license fee for the original IP and a royalty on every chip or wafer produced. In addition to processor IP, ARM Holdings provide a range of tools, physical and systems IP to enable optimized system-on-chip designs. As of 2007, about 98 percent of the more than one billion mobile phones sold each year use at least one ARM processor. As of 2009, ARM processors account for approximately 90% of all embedded 32-bit RISC processors.
The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. ARM processors are developed by ARM and by ARM licensees. Prominent ARM processor families developed by ARM Holdings include the ARM7, ARM9, ARM11 and Cortex. Notable ARM processors developed by licensees include DEC StrongARM, Freescale i.MX, Marvell (formerly Intel) XScale, Nintendo, Nvidia Tegra, ST-Ericsson Nomadik, Qualcomm Snapdragon, the Texas Instruments OMAP product line, the Samsung Hummingbird and the Apple A4.
ARM provides a summary of the numerous vendors who implement ARM cores in their design. KEIL also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM7, ARM9, ARM11, Cortex-M, Cortex-R and Cortex-A device families.
|ARM Family||ARM Architecture||ARM Core||Feature||Cache (I/D), MMU||Typical MIPS @ MHz|
|ARM2||ARMv2||ARM2||ARMv2 added the MUL (multiply) instruction||None||4 MIPS @ 8 MHz
|ARMv2a||ARM250||Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions.||None, MEMC1a||7 MIPS @ 12 MHz|
|ARM3||ARMv2a||ARM3||First integrated memory cache.||4 KB unified||12 MIPS @ 25 MHz
|ARM6||ARMv3||ARM60||ARMv3 first to support 32-bit memory address space (previously 26-bit)||None||10 MIPS @ 12 MHz|
|ARM600||As ARM60, cache and coprocessor bus (for FPA10 floating-point unit).||4 KB unified||28 MIPS @ 33 MHz|
|ARM610||As ARM60, cache, no coprocessor bus.||4 KB unified||17 MIPS @ 20 MHz
|ARM7||ARMv3||ARM700||8 KB unified||40 MHz|
|ARM710||As ARM700, no coprocessor bus.||8 KB unified||40 MHz|
|ARM710a||As ARM710||8 KB unified||40 MHz
|ARM7TDMI||ARMv4T||ARM7TDMI(-S)||3-stage pipeline, Thumb||none||15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
|ARM710T||As ARM7TDMI, cache||8 KB unified, MMU||36 MIPS @ 40 MHz|
|ARM720T||As ARM7TDMI, cache||8 KB unified, MMU with Fast Context Switch Extension||60 MIPS @ 59.8 MHz|
|ARM740T||As ARM7TDMI, cache||MPU|
|ARM7EJ||ARMv5TEJ||ARM7EJ-S||5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions||none|
|ARM8||ARMv4||ARM810||5-stage pipeline, static branch prediction, double-bandwidth memory||8 KB unified, MMU||84 MIPS @ 72 MHz
|StrongARM||ARMv4||SA-1||5-stage pipeline||16 KB/8–16 KB, MMU||203–206 MHz
|ARM9TDMI||ARMv4T||ARM9TDMI||5-stage pipeline, Thumb||none|
|ARM920T||As ARM9TDMI, cache||16 KB/16 KB, MMU with FCSE (Fast Context Switch Extension)||200 MIPS @ 180 MHz|
|ARM922T||As ARM9TDMI, caches||8 KB/8 KB, MMU|
|ARM940T||As ARM9TDMI, caches||4 KB/4 KB, MPU|
|ARM9E||ARMv5TE||ARM946E-S||Thumb, Enhanced DSP instructions, caches||variable, tightly coupled memories, MPU|
|ARM966E-S||Thumb, Enhanced DSP instructions||no cache, TCMs|
|ARM968E-S||As ARM966E-S||no cache, TCMs|
|ARMv5TEJ||ARM926EJ-S||Thumb, Jazelle DBX, Enhanced DSP instructions||variable, TCMs, MMU||220 MIPS @ 200 MHz,|
|ARMv5TE||ARM996HS||Clockless processor, as ARM966E-S||no caches, TCMs, MPU|
|ARM10E||ARMv5TE||ARM1020E||6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP)||32 KB/32 KB, MMU|
|ARM1022E||As ARM1020E||16 KB/16 KB, MMU|
|ARMv5TEJ||ARM1026EJ-S||Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP)||variable, MMU or MPU|
|XScale||ARMv5TE||XScale||7-stage pipeline, Thumb, Enhanced DSP instructions||32 KB/32 KB, MMU||133–400 MHz|
|Bulverde||Wireless MMX, Wireless SpeedStep added||32 KB/32 KB, MMU||312–624 MHz|
|Monahans||Wireless MMX2 added||32 KB/32 KB (L1), optional L2 cache up to 512 KB, MMU||up to 1.25 GHz|
|ARM11||ARMv6||ARM1136J(F)-S||8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions||variable, MMU||740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz|
|ARMv6T2||ARM1156T2(F)-S||9-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructions||variable, MPU|
|ARMv6ZK||ARM1176JZ(F)-S||As ARM1136EJ(F)-S||variable, MMU + TrustZone||965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors|
|ARMv6K||ARM11 MPCore||As ARM1136EJ(F)-S, 1–4 core SMP||variable, MMU|
|Cortex-A||ARMv7-A||Cortex-A5||VFP, NEON, Jazelle RCT, Thumb/Thumb-2, 1–4 cores||variable (L1 + L2), MMU + TrustZone||1.57 DMIPS / MHz per core|
|Cortex-A8||VFP, NEON, Jazelle RCT, Thumb-2, 13-stage superscalar pipeline||variable (L1 + L2), MMU + TrustZone||up to 2 000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)|
|Cortex-A9 MPCore||Application profile, VFPv3 FPU, NEON, Thumb-2, Jazelle RCT/DBX, out-of-order speculative issue superscalar, 1–4 core SMP||32 KB/32 KB L1, up to 4 MB L2, MMU + TrustZone||2.5 DMIPS/MHz per core, 10 000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual core)|
|Cortex-A15 MPCore||Application profile, VFPv4 FPU, NEON, Thumb-2, Jazelle RCT/DBX, out-of-order speculative issue superscalar, Large Physical Address Extensions (LPAE), Hardware virtualization, 1–4 SMP cores||32 KB/32 KB L1, up to 4 MB L2, MMU + TrustZone|
|Cortex-R||ARMv7-R||Cortex-R4(F)||Real-time profile, Thumb-2, (FPU)||variable cache, MPU optional||600 DMIPS @ 475 MHz|
|Cortex-M||ARMv6-M||Cortex-M0||Microcontroller profile, Thumb-2 subset (16-bit Thumb instructions & BL, MRS, MSR, ISB, DSB, and DMB). Hardware multiply instruction optional||No cache.||0.9 DMIPS/MHz|
|Cortex-M1||FPGA targeted, Microcontroller profile, Thumb-2 subset (16-bit Thumb instructions & BL, MRS, MSR, ISB, DSB, and DMB).||None, tightly coupled memory optional.||Up to 136 DMIPS @ 170 MHz (0.8 DMIPS/MHz, MHz achievable FPGA-dependent)|
|ARMv7-M||Cortex-M3||Microcontroller profile, Thumb-2 only. Hardware divide instruction.||no cache, MPU optional.||125 DMIPS @ 100 MHz|
|ARMv7-ME||Cortex-M4||Microcontroller profile, both Thumb and Thumb-2, FPU. Hardware MAC, SIMD and divide instructions.||MPU optional.||1.25 DMIPS/MHz|
|ARM Family||ARM Architecture||ARM Core||Feature||Cache (I/D), MMU||Typical MIPS @ MHz|
Example applications of ARM cores
|ARM1||ARM1||ARM Evaluation System second processor for BBC Micro|
|ARM2||ARM2||Acorn Archimedes, Chessmachine|
|ARM60||ARM60||3DO Interactive Multiplayer, Zarlink GPS Receiver|
|ARM610||ARM610||Acorn Risc PC 600, Apple Newton 100 series|
|ARM700||ARM700||Acorn Risc PC prototype CPU card|
|ARM710||ARM710||Acorn Risc PC 700|
|ARM710a||ARM7100, ARM 7500 and ARM7500FE||Acorn Risc PC 700, Apple eMate 300, Psion Series 5 (ARM7100), Acorn A7000 (ARM7500), Acorn A7000+ (ARM7500FE), Network Computer (ARM7500FE)|
|ARM7TDMI(-S)||Atmel AT91SAM7, NXP Semiconductors LPC2000 and LH754xx, Actel CoreMP7||Game Boy Advance, Nintendo DS, Apple iPod, Lego NXT, Juice Box, Garmin Navigation Devices (1990s – early 2000s)|
|ARM710T||Psion Series 5mx, Psion Revo/Revo Plus/Diamond Mako|
|ARM720T||NXP Semiconductors LH7952x||Zipit Wireless Messenger|
|StrongARM||Digital SA-110, SA-1100, SA-1110|
|ARM810||Acorn Risc PC prototype CPU card|
|ARM920T||Atmel AT91RM9200, AT91SAM9, Cirrus Logic EP9302, EP9307, EP9312, EP9315, Samsung S3C2442 and S3C2410||Armadillo, GP32, GP2X (first core), Tapwave Zodiac (Motorola i.MX1), Hewlett-Packard HP-49/50 Calculators, Sun SPOT, HTC TyTN, FIC Neo FreeRunner), Garmin Navigation Devices (mid–late 2000s), TomTom navigation devices|
|ARM922T||NXP Semiconductors LH7A40x|
|ARM940T||GP2X (second core), Meizu M6 Mini Player|
|ARM926EJ-S||Texas Instruments OMAP1710, OMAP1610, OMAP1611, OMAP1612, OMAP-L137, OMAP-L138; Qualcomm MSM6100, MSM6125, MSM6225, MSM6245, MSM6250, MSM6255A, MSM6260, MSM6275, MSM6280, MSM6300, MSM6500, MSM6800; Freescale i.MX21, i.MX27, Atmel AT91SAM9, NXP Semiconductors, Samsung S3C2412 LPC30xx, NEC C10046F5-211-PN2-A SoC – undocumented core in the ATi Hollywood graphics chip used in the Wii, Telechips TCC7801, TCC7901, ZiiLABS ZMS-05, Rockchip RK2806 and RK2808, NeoMagic MiMagic Family MM6, MM6+, MM8, MTV.||Mobile phones: Sony Ericsson (K, W series); Siemens and Benq (x65 series and newer); LG Arena; GPH Wiz; Squeezebox Duet Controller (Samsung S3C2412). Squeezebox Radio; Buffalo TeraStation Live (NAS); Drobo FS (NAS); Western Digital MyBook I World Edition; Western Digital MyBook II World Edition; Seagate FreeAgent DockStar STDSD10G-RK; Seagate FreeAgent GoFlex Home; Chumby Classic|
|ARM946E-S||Nintendo DS, Nokia N-Gage, Canon PowerShot A470, Canon EOS 5D Mark II, Conexant 802.11 chips, Samsung S5L2010|
|ARM968E-S||NXP Semiconductors LPC29xx|
|ARM1026EJ-S||Conexant so4610 and so4615 ADSL SoC|
|XScale||Intel 80200, 80219, PXA210, PXA250, PXA255, PXA263, PXA26x, PXA27x, PXA3xx, PXA900, IXC1100, IXP42x||
|ARM1136J(F)-S||Texas Instruments OMAP2420, Qualcomm MSM7200, MSM7201A, MSM7227, Freescale i.MX31 and MXC300-30||
|ARM1176JZ(F)-S||Conexant CX2427X, Nvidia GoForce 6100; Telechips TCC9101, TCC9201, TCC8900, Fujitsu MB86H60, Samsung S3C6410, S3C6430, Qualcomm MSM7627, Infineon X-GOLD 213||Apple iPhone (original and 3G), Apple iPod touch (1st and 2nd Generation), Motorola RIZR Z8, Motorola RIZR Z10, Nintendo 3DS|
|ARM11 MPCore||Nvidia APX 2500 (Tegra)|
|Cortex-A8||Texas Instruments OMAP3xxx series, FreeScale i.MX51-SOC, Apple A4, ZiiLABS ZMS-08, Samsung Hummingbird S5PC110 , Qualcomm Snapdragon QSD8x50(A)/MSM7x30/MSM8255||HTC Desire, SBM7000, Oregon State University OSWALD, Gumstix Overo Earth, Pandora, Apple iPhone 3GS, Apple iPod touch (3rd and 4th Generation), Apple iPad (A4), Apple iPhone 4 (A4), Archos 5, BeagleBoard, Motorola Droid, Motorola Droid X, Motorola Droid 2, Motorola Droid R2D2 Edition, Palm Pre, Samsung Omnia HD, Samsung Wave S8500, Samsung i9000 Galaxy S, Sony Ericsson Satio, Touch Book, Nokia N900, Meizu M9, Google Nexus S, Sharp PC-Z1 "Netwalker".|
|Cortex-A9||Texas Instruments OMAP4430/4440, ST-Ericsson U8500 / U5500, Nvidia Tegra2, Qualcomm Snapdragon QSD8672/MSM8260/MSM8660, Samsung Orion, STMicroelectronics SPEAr1310, Xilinx Extensible Processing Platform, Trident PNX847x/8x/9x STB SoC, Freescale i.MX6 ||LG Optimus 2X, Motorola Atrix 4G,Motorola DROID BIONIC|
|Cortex-A15||Qualcomm Snapdragon MSM8270/MSM8960, Texas Instruments OMAP5, Samsung, ST Ericsson Nvidia|
|Cortex-R4(F)||Broadcom, Texas Instruments TMS570|
|Cortex-M0||NXP Semiconductors LPC11xx, Triad Semiconductor, Melfas, Chungbuk Technopark, Nuvoton, austriamicrosystems, Rohm|
|Cortex-M1||Actel ProASIC3, ProASIC3L, IGLOO and Fusion PSC devices, Altera Cyclone III, other FPGA products are also supported e.g. Synplicity|
|Cortex-M3||Texas Instruments Stellaris, STMicroelectronics STM32, NXP Semiconductors LPC17xx, Toshiba TMPM330, Ember EM3xx, Atmel AT91SAM3, Europe Technologies EasyBCU, Energy Micro EFM32, Actel SmartFusion, mbed microcontroller|
|Cortex-M4||Freescale Kinetis, NXP Semiconductors LCP4300, STMicroelectronics|
From 1995 onwards, the ARM Architecture Reference Manual has been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and starting with the Cortex series of cores, three "profiles" are defined:
- "Application" profile: Cortex-A series
- "Real-time" profile: Cortex-R series
- "Microcontroller" profile: Cortex-M series
Profiles are allowed to subset the architecture. For example the ARMv7-M profile used by the Cortex-M3 core is notable in that it supports only the Thumb-2 instruction set, and the ARMv6-M profile (used by the Cortex-M0) is a subset of the ARMv7-M profile (supporting fewer instructions).
Pipelines and other implementation issues
The ARM7 and earlier implementations have a three stage pipeline; the stages being fetch, decode, and execute. Higher performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster adder, and more extensive branch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier (hence the added "M").
The architecture provides a non-intrusive way of extending the instruction set using "coprocessors" which can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and MMU operation (on processors that have one).
In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space or into the coprocessor space or connecting to another device (a bus) which in turn attaches to the processor. Coprocessor accesses have lower latency so some peripherals (for example XScale interrupt controller) are designed to be accessible in both ways (through memory and through coprocessors). In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialized operations to support a specific set of HDTV transcoding primitives.
All modern ARM processors include hardware debugging facilities; without them, software debuggers could not perform basic operations like halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de-facto debug standard, although it was not architecturally guaranteed.
The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints, and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.
There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.
DSP enhancement instructions
To improve the ARM architecture for digital signal processing and multimedia applications, a few new instructions were added to the set. These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I.
To improve compiled code-density, processors since the ARM7TDMI have featured the Thumb instruction set state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a variable-length instruction set providing 32-bit and 16-bit instructions. Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state.
In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.
Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16 bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory.
The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, including XScale, have included a Thumb instruction decoder.
VFP (Vector Floating Point) technology is a coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture also supports execution of short vector instructions but these operate on each vector element sequentially and thus do not offer the performance of true SIMD (Single Instruction Multiple Data) parallelism. This mode can still be useful in graphics and signal-processing applications, however, as it allows a reduction in code size and instruction fetch and decode overhead.
Advanced SIMD (NEON)
The Advanced SIMD extension, marketed as NEON technology, is a combined 64- and 128-bit single instruction multiple data (SIMD) instruction set that provides standardized acceleration for media and signal processing applications. NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM AMR (Adaptive Multi-Rate) speech codec at no more than 13 MHz. It features a comprehensive instruction set, separate register files and independent execution hardware. NEON supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data and operates in SIMD operations for handling audio and video processing as well as graphics and gaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardware shares the same floating-point registers as used in VFP.
Embedded operating systems
The ARM architecture is supported by a large number of embedded and real-time operating systems, including Windows CE, Symbian OS, FreeRTOS, eCos, INTEGRITY, Nucleus PLUS, MicroC/OS-II, QNX, RTXC Quadros, ThreadX and VxWorks.
The following Linux distributions support ARM processors:
- Arch Linux
- Chrome OS
- T2 SDE
- Wind River Linux
The following BSD derivatives support ARM processors:
Microsoft announced on 5 January 2011 that the next major version of the Windows NT family will include support for ARM processors. Microsoft demonstrated a preliminary version of Windows (version 6.2.7867) running on an ARM-based computer at the 2011 Consumer Electronics Show.
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