Talk:X86: Difference between revisions
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The first and fourth sections of this article are both named "Overview". The first one provides some background information and description of modern implementation mostly in layman's terms, while the other goes into technical details. |
The first and fourth sections of this article are both named "Overview". The first one provides some background information and description of modern implementation mostly in layman's terms, while the other goes into technical details. |
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== I Require The Table in the Main Article to Be Removed! == |
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It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement! --- Aaron Janagewen <!-- Template:Unsigned IP --><small class="autosigned">— Preceding [[Wikipedia:Signatures|unsigned]] comment added by [[Special:Contributions/221.9.17.84|221.9.17.84]] ([[User talk:221.9.17.84#top|talk]]) 22:08, 1 October 2018 (UTC)</small> <!--Autosigned by SineBot--> |
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== Semi-protected edit request on 1 October 2018 == |
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{{edit semi-protected|X86|answered=yes}} |
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It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement! --- Aaron Janagewen [[Special:Contributions/221.9.17.84|221.9.17.84]] ([[User talk:221.9.17.84|talk]]) 22:11, 1 October 2018 (UTC) |
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: [[File:Red information icon with gradient background.svg|20px|link=|alt=]] '''Not done:''' please establish a [[Wikipedia:Consensus|consensus]] for this alteration '''[[Wikipedia:Edit requests|before]]''' using the {{tlx|edit semi-protected}} template.<!-- Template:ESp --> [[User:RudolfRed|RudolfRed]] ([[User talk:RudolfRed|talk]]) 22:48, 1 October 2018 (UTC) |
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== Semi-protected edit request on 2 October 2018 == |
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{{edit semi-protected|X86|answered=no}} |
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It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement! |
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I require the table on the section ''Chronology'' getting back to its previous version, as below |
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{| class="wikitable sortable" style="text-align: center;" |
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|- |
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! First introduced |
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! Prominent CPU brands |
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! Linear address size (bits) |
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! Segment / offset size (bits) |
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! Physical address size (bits) |
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! Notable (new) features |
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|- |
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| 1978 || [[Intel 8086]], [[Intel 8088]] and clones || style="background: #FAECC8;" | 16 || {{N/A}} || 20 || First x86 microprocessors |
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|- |
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| 1982 || [[Intel 80186]], [[Intel 80188]] and clones, [[NEC V20]]/V30 || style="background: #FAECC8;" | 16 || {{N/A}} || 20 || Hardware for fast [[Memory address|address]] calculations, fast multiplication and division |
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|- |
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| 1982 || [[Intel 80286]] and clones || style="background: #FAECC8;" | 16 || 14 / 16 || 24 || [[memory management unit|MMU]], for [[protected mode]] and a larger [[address space]] |
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|- |
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| 1985 || [[Intel 80386]] and clones, [[AMD Am386]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 || [[32-bit]] [[instruction set]], MMU with paging, PGA132 socket |
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|- |
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| 1989 || [[Intel 80486]] and clones, [[AMD Am486]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 || RISC-like [[pipelining]], integrated [[x87]] [[Floating point unit|FPU]] (80-bit), on-chip [[CPU cache|cache]], PGA168 socket |
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|- |
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| 1992 || [[Cyrix Cx486SLC]], [[Cyrix Cx486DLC]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 || L1 cache and pipelining introduced into the 386 platform, PGA132 socket |
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|- |
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| 1993 || [[P5 (microarchitecture)|Pentium]], [[Pentium MMX]], [[Rise Technology|Rise]] [[mP6]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 || [[Superscalar]], [[64-bit]] [[Bus (computing)|databus]], faster FPU, [[MMX (instruction set)|MMX]] (2× 32-bit), [[Socket 7]], [[Symmetric multiprocessing|SMP]] |
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|- |
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| 1995 || [[Pentium Pro]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 36 ([[Physical Address Extension|PAE]]) || µ-op translation, conditional move instructions, [[Out-of-order execution|out-of-order]], [[register renaming]], [[speculative execution]], [[Physical Address Extension|PAE]] (Pentium Pro), in-package [[L2 cache]] (Pentium Pro), [[Socket 8]] |
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|- |
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| 1996 || [[AMD K5]], [[Cyrix 6x86]], [[Cyrix MII]], [[Nx586|Nx586 (1994)]], [[Integrated Device Technology|IDT]]/[[Centaur Technology|Centaur]]-[[WinChip|C6]], [[Cyrix III]]-Samuel (2000), [[VIA C3]]-Samuel2 / VIA C3-Ezra (2001) || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 || Discrete microarchitecture (µ-op translation) |
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|- |
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| 1997 || [[Am5x86]], [[Cyrix 5x86]], [[Pentium OverDrive]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 || Partial Pentium's specification brought into the 486 platform |
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|- |
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| 1997 || [[Pentium II]]/[[Pentium III|III]], [[Celeron]], [[Xeon]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 36 ([[Physical Address Extension|PAE]]) || [[Streaming SIMD Extensions|SSE]] (2× 64-bit), on-die L2 Cache ([[Celeron#Mendocino|Mendocino]], [[Pentium III#Coppermine|Coppermine]]), [[Slot 1|SLOT 1]] or [[Socket 370]] |
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|- |
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| 1997 || [[AMD K6]]/[[AMD K6-2|2]]/[[AMD K6-III|III]], [[Cyrix III]]-Joshua (2000)|| style="background: #CEE0F2;" | 32 || 14 / 32 || 32 ||On-die L2-Cache ([[K6-III]], Cyrix III Joshua), [[3DNow!]], no PAE support, [[Super Socket 7]] (K6-2) |
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|- |
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| 1999 || [[Athlon]], [[Athlon XP]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 36 ([[Physical Address Extension|PAE]]<ref name="Athlon PAE"/>)|| Superscalar FPU, wide design (up to three x86 instr./clock), [[Slot A]] or [[Socket A]], [[Symmetric multiprocessing|SMP]] |
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|- |
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| 2000 || [[Pentium 4]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 36 ([[Physical Address Extension|PAE]]) || Deeply [[pipelining|pipelined]], 20 pipeline stages, Intel [[VT-x]], Rapid Execution Engine, Execution Trace Cache, [[Replay system]], Quad-Pumped Front-Side Bus, high frequency, [[SSE2]], [[hyper-threading]], [[Socket 478]] |
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|- |
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| 2000 || [[Transmeta Crusoe]], [[Transmeta Efficeon]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 || [[Very long instruction word|VLIW]] design with x86 [[emulator]], on-die memory controller |
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|- |
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| 2001 || Intel [[Itanium]] IA-32 compatibility mode || style="background: #CEE0F2;" | 32 || 14 / 32 || N/A || [[Explicitly parallel instruction computing|EPIC]] architecture with an on-package engine (pre-2006 chips, later using [[IA-32 Execution Layer]]) that provides backward support for most IA-32 applications |
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|- |
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| 2003 || [[Pentium M]], [[VIA C7]] (2005), [[Intel Core]] (2006)<!-- Intel Core is based off Pentium M --> || style="background: #CEE0F2;" | 32 || 14 / 32 || 36 ([[Physical Address Extension|PAE]])|| Optimized for low [[thermal design power]], four pumped FSB, [[Micro-op fusion|μ-op fusion]] |
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|- |
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| 2003 || [[Athlon 64]], [[Athlon 64 X2]] (2005), [[Sempron]] (2004), [[Opteron]] || style="background: #CEF2E0;" | 64 || {{N/A}} || 36 (Athlon FX, Sampron)/40 (Opteron) || [[AMD64]] processor (excluding 32-bit Sempron), on-die memory controller, [[HyperTransport]], [[Multi-core processor|CMP]], virtualization ([[AMD-V]]) on some models, [[Socket 754]]/[[Socket 939|939]]/[[Socket 940|940]] or [[Socket AM2|AM2]] socket |
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|- |
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| 2005 || [[Pentium4#Prescott|Pentium 4 Prescott]] F/506/516/5x1/6xx, [[Celeron D]] 3x1/3x6/355, [[Pentium D]] ||style="background: #CEF2E0;" | 64 || {{N/A}} || 36 || [[EM64T]] technology introduced, very deeply [[pipelining|pipelined]], 31 pipeline stages, high frequency, [[SSE3]], [[LGA 775]] socket, [[Multi-core processor|CMP]], [[x86-64]] |
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|- |
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| 2006 || [[Intel Core 2]] || style="background: #CEF2E0;" | 64 || {{N/A}} || 36 (Intel Core 2,<ref>{{cite web|url=http://download.intel.com/design/processor/datashts/318732.pdf|title=Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet|page=66|publisher=Intel|date=June 2009}}</ref> Xeon 5100 <ref>{{cite web|url=http://www.intel.com/Assets/PDF/datasheet/313355.pdf|title=Dual-Core Intel Xeon Processor 5100 Series Datasheet|page=24|publisher=Intel|date=August 2007}}</ref>/40 (Xeon 7200/7300 on LGA771<ref>{{cite web|url=http://www.intel.com/Assets/en_US/PDF/datasheet/318080.pdf|title=Intel Xeon Processor 7200 Series and 7300 Series Datasheet|page=87|publisher=Intel|date=September 2008}}</ref>) ||[[Intel 64]] processor, low power, [[multi-core]], lower clock frequency, [[SSE4]] (Penryn), wide dynamic execution, µ-op fusion, macro-µ-op fusion, virtualization ([[Intel VT]]) on some models |
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|- |
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| 2007 || [[Vortex86|DM&P Vortex86]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 36 || in-order core with high pipeline, deep integrated with sound&graphic unit(SoC), on-chip memory controller, low clock, low power for embedded use |
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| 2007 || [[Phenom (processor)|AMD Phenom]], [[AMD Phenom II]] (2008) || style="background: #CEF2E0;" | 64 || {{N/A}} || 40 (Phenom, Athlon, Sampron)/48 (Phenom II, Opteron)|| Monolithic quad-core, [[SSE4a]], HyperTransport 3, [[AM2+]] or [[AM3]] socket |
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|- |
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| 2008 || [[VIA Nano]] || style="background: #CEF2E0;" | 64 || {{N/A}} || 36 || [[Out-of-order execution|Out-of-order]], superscalar, 64-bit (integer CPU), [[hardware-based encryption]]; very low power; adaptive [[power management]] |
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|- |
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| 2008 || 1st gen. [[Intel Core i3]], [[Core i5|i5]] and [[Core i7|i7]] ([[Nehalem (microarchitecture)|Nehalem]] and [[Westmere (microarchitecture)|Westmere]]) || style="background: #CEF2E0;" | 64 || {{N/A}} || 40 || Hyper-Threading, [[Intel Turbo Boost]] 1.0, [[AES-NI]], [[Out-of-order execution|Out-of-order]], QuickPath, native memory controller, on-die L3 cache, modular, [[Intel HD Graphics]] introduced onto CPU chip ([[Clarkdale (microprocessor)|Clarkdale]]), [[LGA 1366]] (Nehalem) or [[LGA 1156]] socket |
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|- |
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| 2008 || [[Intel Atom]] || style="background: #CEE0F2;" | 32 || 14 / 32 || 32 (Bonnell) 36 (Bay Trailer and later) || In-order but highly pipelined, very-low-power, some models ([[Bonnell (microarchitecture)#Diamondville microprocessor|Diamondville]]) with 32-bit (integer CPU), on-die GPU ([[Bonnell (microarchitecture)#Pineview microprocessor|Penwell]], [[Bonnell (microarchitecture)#Cedarview microprocessor|Cedarview]]) |
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|- |
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| 2010 || [[Bulldozer (microarchitecture)|AMD FX]] || style="background: #CEF2E0;" | 64 || {{N/A}} || 48 (FX) 52(Opteron)|| highly pipelined, about 20 stages long pipeline, very-power hungry, very high clock, share instruction cache and FlexFPU between two cores in the [[Multi-chip module|module]], first consumer octa-core processor, CMT (Clustered Multi-Thread), FMA, OpenCL, support up to 64 socket per chipset. |
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|- |
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| 2011 || AMD APU C, E and Z Series ([[Bobcat (processor)|Bobcat]]) ||style="background: #CEF2E0;" | 64 || {{N/A}} || 36 || [[Out-of-order execution|Out-of-order]], 64-bit (integer CPU), on-die GPU; low power (Bobcat), [[Socket FM1]] (Desktop) |
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|- |
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| 2011 || AMD APU A and E Series ([[AMD Fusion|Llano]]) || style="background: #CEF2E0;" | 64 || {{N/A}} || 40 || on-die GPU, first generation fusion APU |
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|- |
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| 2011 || AMD APU A Series ([[Bulldozer (processor)|Bulldozer, Trinity]] and later) || style="background: #CEF2E0;" | 64 || {{N/A}} || 48 || [[SSE5]]/[[Advanced Vector Extensions|AVX]] (4× 64-bit), highly modular design, integrated on-die [[Graphics processing unit|GPU]], [[Socket FM2]] or [[Socket FM2+]], [[General-purpose computing on graphics processing units|GPGPU]] |
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|- |
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| 2011 || 2nd and 3rd gen. [[Intel Core i3]], [[Core i5|i5]] and [[Core i7|i7]] ([[Sandy Bridge (microarchitecture)|Sandy Bridge]] and [[Ivy Bridge (microarchitecture)|Ivy Bridge]])|| style="background: #CEF2E0;" | 64 || {{N/A}} || 42 || Internal Ring connection, Intel Turbo Boost 2.0, [[F16C]]<ref>{{cite web|url=https://blogs.msdn.microsoft.com/chuckw/2012/09/11/directxmath-f16c-and-fma/|title=DirectXMath: F16C and FMA|author=Chuck Walbourn|date=September 11, 2012|website=Games for Windows and the DirectX SDK blog|publisher=Microsoft}}</ref> [[Advanced Vector Extensions|AVX]], GPGPU, [[Micro-operation cache]](Uop Cache), relatively long pipeline (14 to 19 stages),<ref>{{cite web|url=http://www.anandtech.com/show/6355/intels-haswell-architecture/6|title=Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel|at=The Haswell Front End|author= Anand Lal Shimpi|date=October 5, 2012|website=[[Anandtech]]}}</ref>[[LGA 1155]] socket. |
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|- |
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| 2012 || Intel [[Xeon Phi]] ([[Larrabee (microarchitecture)|Larrabee]]) || style="background: #CEF2E0" | 64 || {{N/A}} || 36 || [[Xeon Phi|many integrated core]] (MIC) architecture (w/62), in-order [[P5 (microarchitecture)|P54C]] with x86-64, very wide [[vector processing|vector unit]], LRBni instructions (8× 64-bit), four threads per core. |
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|- |
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| 2013 || 4th and 5th gen. [[Intel Core i3]], [[Core i5]] and [[Core i7]] ([[Haswell (microarchitecture)|Haswell]] and [[Broadwell (microarchitecture)|Broadwell]]) || style="background: #CEF2E0;" | 64 || {{N/A}} || 44 || [[Advanced Vector Extensions 2|AVX2]], [[FMA instruction set|FMA3]], [[Transactional Synchronization Extensions|TSX]], [[Bit Manipulation Instruction Sets|BMI1, BMI2 and ABM]] instructions, [[Intel ADX]], [[Fully integrated voltage regulator]] (FIVR), Intel Turbo Boost 3.0 Max(Broadwell-E), high clock rate, [[LGA 1150]] or [[LGA 2011]] socket |
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|- |
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| 2015 || 6th, 7th and 8th gen. [[Intel Core i3]], [[Core i5|i5]], [[Core i7|i7]] and [[Core i9|i9]] ([[Skylake (microarchitecture)|Skylake]], [[Kaby Lake]] and [[Coffee Lake]])|| style="background: #CEF2E0;" | 64 || {{N/A}} || 46 || [[Out-of-order execution|Out-of-order]], 64-bit (integer CPU), [[AVX-512]], [[Intel SGX]], [[Intel MPX]], high clock rate, integrated on-die [[Southbridge (computing)|southbridge]], integrated on-die x86 MIC array [[Graphics processing unit|GPU]], [[System on a chip|SoC]], [[Many Integrated Core|MIC]], [[LGA 1151]] socket. |
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|2017 |
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|[[Ryzen|AMD Ryzen]] 3, Ryzen 5, Ryzen 7 and Ryzen Threadripper ([[Zen (microarchitecture)|Zen]] and [[Zen+]]) |
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|style="background: #CEF2E0;" | 64 |
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|{{N/A}} |
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|48 |
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|Multiple CCXs connected through infinity Fabric<ref>{{Cite news|url=https://www.anandtech.com/show/11170/the-amd-zen-and-ryzen-7-review-a-deep-dive-on-1800x-1700x-and-1700/9|title=The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700|last=Cutress|first=Ian|access-date=2018-03-24}}</ref>, eXtended Frequency Range (XFR)<ref>{{Cite web|url=https://www.pcper.com/news/Processors/PSA-AMD-XFR-Enabled-All-Ryzen-CPUs-X-SKUs-Have-Wider-Range|title=PSA: AMD XFR Enabled On All Ryzen CPUs, X SKUs Have Wider Range {{!}} PC Perspective|last=Verry|first=Tim|date=4 March 2017|website=www.pcper.com|language=en|archive-url=|archive-date=|dead-url=|access-date=2018-03-24}}</ref>, SenseMI, Simultaneous Multi Threading (SMT)<ref>{{Cite news|url=https://www.anandtech.com/show/11170/the-amd-zen-and-ryzen-7-review-a-deep-dive-on-1800x-1700x-and-1700|title=The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700|last=Cutress|first=Ian|access-date=2018-03-24}}</ref>, [[Socket AM4|AM4]]/[[Socket TR4|TR4]] Socket |
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|- |
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! First introduced |
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! Prominent CPU brands |
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! Linear address size (bits) |
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! Segment / offset size (bits) |
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! Physical address size (bits) |
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! Notable (new) features |
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|} |
Revision as of 01:05, 2 October 2018
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"Generation" column again
How did this completely unreferenced bit of stuff-someone-made-up-one-day get back in here?
This is how: https://en.wikipedia.org/w/index.php?title=X86&type=revision&diff=844673781&oldid=843473014 Another Janagewen IP sock.
It's going away. There is no reference for industry-wide "generation" numbers. Jeh (talk) 19:32, 19 July 2018 (UTC)
Fixed: Large number of problems in the chronology table
Hello.
I fixed a large number of problems in the Chronology section. Here is a detailed list of what has gotten fixed:
- Erroneous info: IA-64 and ARM64 were framed into the chronology, in a way that implied they were implementations of x86! And that's the smallest problem; this integration was so weird, it was analogous to reading an article on the life of Bill Gates that frequently strayed off the topic to explain the details of Beyonce's life in parallel. Whatever the noble motive of the original writer, the end result grossly failed to justify itself.
- Writer's pet peeves: Apparently the writer had felt the need to emphatically explain that "x64" is part of "x86". But the irony is this act would backfire because the integration of erroneous info about IA-64 and ARM64. It is like the story of the boy called wolf for the third time; when you (by mistake or intentionally) tell people that IA-64 and ARM64 are part of x86, and they find out otherwise, they don't believe you when you tell them x64 is an x86 version.
- Ambiguous info: Intel Core i3, i5 and i7 are CPU brand names, not CPU models; these brand names have been used since 2008 for the bulk of Intel products. I replaced them with the Intel CPU architecture names, e.g., Nehalem.
- Conflicting top and bottom headings:
- "Generation" ≠ "Era" (one is time, one is the product of it)
- "Introduction" ≠ "Release" (one happens once, the other can happen repeatedly afterwards)
- "Prominent CPU models" ≠ "CPU models" (not every CPU is prominent)
- "Address Space" ≠ "Physical Address Space", especially when right below the former, it says "Physical", "virtual" and "linear"
- "Notable features" ≠ "New features" (one feature can be new but not notable)
- Contested info: Please read previous discussions in this talk page
- Editorializing (e.g. "Enhanced Platform", which is zero-informative. Proof: [1])
- Broken links
- Incorrect use of slash; see MOS:SLASH
- Capitalization; see MOS:CAPS
- "NA" → "{{N/A}}"
5.78.104.231 (talk) 08:35, 28 August 2018 (UTC)
@5.78.104.231: I've no comments about your words, but would you please design or devise completely a new table rather than modifying mine? 221.9.14.156 (talk) 23:32, 4 September 2018 (UTC)
- You (221.9.14.156) are quite obviously the long-permanent-blocked Janagewen (see user:Janagewen, WP:Sockpuppet_investigations/Janagewen/Archive, etc.). You are permanently blocked from editing due to a wide variety of problems, as detailed at your various case pages. I have therefore reverted your change and will continue to do so. Jeh (talk) 00:51, 5 September 2018 (UTC)
Two "Overview" sections
The first and fourth sections of this article are both named "Overview". The first one provides some background information and description of modern implementation mostly in layman's terms, while the other goes into technical details.
I Require The Table in the Main Article to Be Removed!
It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement! --- Aaron Janagewen — Preceding unsigned comment added by 221.9.17.84 (talk) 22:08, 1 October 2018 (UTC)
Semi-protected edit request on 1 October 2018
![]() | This edit request has been answered. Set the |answered= or |ans= parameter to no to reactivate your request. |
It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement! --- Aaron Janagewen 221.9.17.84 (talk) 22:11, 1 October 2018 (UTC)
Not done: please establish a consensus for this alteration before using the
{{edit semi-protected}}
template. RudolfRed (talk) 22:48, 1 October 2018 (UTC)
Semi-protected edit request on 2 October 2018
![]() | It is requested that an edit be made to the semi-protected article at X86. (edit · history · last · links · protection log)
This template must be followed by a complete and specific description of the request, that is, specify what text should be removed and a verbatim copy of the text that should replace it. "Please change X" is not acceptable and will be rejected; the request must be of the form "please change X to Y".
The edit may be made by any autoconfirmed user. Remember to change the |
It cost me lots of time to design a table like https://fr.wikipedia.org/w/index.php?title=Discussion:X86&oldid=144373066, and I put it on the main article several months ago, attacked by some a so called Computer professional, but a really minor! And right now this table was modified and goes away too far from my initial design purposes, so I require the table in the main article to be removed! Anyone could put the old one there, but please do not change mine!!! I do really require this requirement!
I require the table on the section Chronology getting back to its previous version, as below
First introduced | Prominent CPU brands | Linear address size (bits) | Segment / offset size (bits) | Physical address size (bits) | Notable (new) features |
---|---|---|---|---|---|
1978 | Intel 8086, Intel 8088 and clones | 16 | — | 20 | First x86 microprocessors |
1982 | Intel 80186, Intel 80188 and clones, NEC V20/V30 | 16 | — | 20 | Hardware for fast address calculations, fast multiplication and division |
1982 | Intel 80286 and clones | 16 | 14 / 16 | 24 | MMU, for protected mode and a larger address space |
1985 | Intel 80386 and clones, AMD Am386 | 32 | 14 / 32 | 32 | 32-bit instruction set, MMU with paging, PGA132 socket |
1989 | Intel 80486 and clones, AMD Am486 | 32 | 14 / 32 | 32 | RISC-like pipelining, integrated x87 FPU (80-bit), on-chip cache, PGA168 socket |
1992 | Cyrix Cx486SLC, Cyrix Cx486DLC | 32 | 14 / 32 | 32 | L1 cache and pipelining introduced into the 386 platform, PGA132 socket |
1993 | Pentium, Pentium MMX, Rise mP6 | 32 | 14 / 32 | 32 | Superscalar, 64-bit databus, faster FPU, MMX (2× 32-bit), Socket 7, SMP |
1995 | Pentium Pro | 32 | 14 / 32 | 36 (PAE) | µ-op translation, conditional move instructions, out-of-order, register renaming, speculative execution, PAE (Pentium Pro), in-package L2 cache (Pentium Pro), Socket 8 |
1996 | AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III-Samuel (2000), VIA C3-Samuel2 / VIA C3-Ezra (2001) | 32 | 14 / 32 | 32 | Discrete microarchitecture (µ-op translation) |
1997 | Am5x86, Cyrix 5x86, Pentium OverDrive | 32 | 14 / 32 | 32 | Partial Pentium's specification brought into the 486 platform |
1997 | Pentium II/III, Celeron, Xeon | 32 | 14 / 32 | 36 (PAE) | SSE (2× 64-bit), on-die L2 Cache (Mendocino, Coppermine), SLOT 1 or Socket 370 |
1997 | AMD K6/2/III, Cyrix III-Joshua (2000) | 32 | 14 / 32 | 32 | On-die L2-Cache (K6-III, Cyrix III Joshua), 3DNow!, no PAE support, Super Socket 7 (K6-2) |
1999 | Athlon, Athlon XP | 32 | 14 / 32 | 36 (PAE[1]) | Superscalar FPU, wide design (up to three x86 instr./clock), Slot A or Socket A, SMP |
2000 | Pentium 4 | 32 | 14 / 32 | 36 (PAE) | Deeply pipelined, 20 pipeline stages, Intel VT-x, Rapid Execution Engine, Execution Trace Cache, Replay system, Quad-Pumped Front-Side Bus, high frequency, SSE2, hyper-threading, Socket 478 |
2000 | Transmeta Crusoe, Transmeta Efficeon | 32 | 14 / 32 | 32 | VLIW design with x86 emulator, on-die memory controller |
2001 | Intel Itanium IA-32 compatibility mode | 32 | 14 / 32 | N/A | EPIC architecture with an on-package engine (pre-2006 chips, later using IA-32 Execution Layer) that provides backward support for most IA-32 applications |
2003 | Pentium M, VIA C7 (2005), Intel Core (2006) | 32 | 14 / 32 | 36 (PAE) | Optimized for low thermal design power, four pumped FSB, μ-op fusion |
2003 | Athlon 64, Athlon 64 X2 (2005), Sempron (2004), Opteron | 64 | — | 36 (Athlon FX, Sampron)/40 (Opteron) | AMD64 processor (excluding 32-bit Sempron), on-die memory controller, HyperTransport, CMP, virtualization (AMD-V) on some models, Socket 754/939/940 or AM2 socket |
2005 | Pentium 4 Prescott F/506/516/5x1/6xx, Celeron D 3x1/3x6/355, Pentium D | 64 | — | 36 | EM64T technology introduced, very deeply pipelined, 31 pipeline stages, high frequency, SSE3, LGA 775 socket, CMP, x86-64 |
2006 | Intel Core 2 | 64 | — | 36 (Intel Core 2,[2] Xeon 5100 [3]/40 (Xeon 7200/7300 on LGA771[4]) | Intel 64 processor, low power, multi-core, lower clock frequency, SSE4 (Penryn), wide dynamic execution, µ-op fusion, macro-µ-op fusion, virtualization (Intel VT) on some models |
2007 | DM&P Vortex86 | 32 | 14 / 32 | 36 | in-order core with high pipeline, deep integrated with sound&graphic unit(SoC), on-chip memory controller, low clock, low power for embedded use |
2007 | AMD Phenom, AMD Phenom II (2008) | 64 | — | 40 (Phenom, Athlon, Sampron)/48 (Phenom II, Opteron) | Monolithic quad-core, SSE4a, HyperTransport 3, AM2+ or AM3 socket |
2008 | VIA Nano | 64 | — | 36 | Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption; very low power; adaptive power management |
2008 | 1st gen. Intel Core i3, i5 and i7 (Nehalem and Westmere) | 64 | — | 40 | Hyper-Threading, Intel Turbo Boost 1.0, AES-NI, Out-of-order, QuickPath, native memory controller, on-die L3 cache, modular, Intel HD Graphics introduced onto CPU chip (Clarkdale), LGA 1366 (Nehalem) or LGA 1156 socket |
2008 | Intel Atom | 32 | 14 / 32 | 32 (Bonnell) 36 (Bay Trailer and later) | In-order but highly pipelined, very-low-power, some models (Diamondville) with 32-bit (integer CPU), on-die GPU (Penwell, Cedarview) |
2010 | AMD FX | 64 | — | 48 (FX) 52(Opteron) | highly pipelined, about 20 stages long pipeline, very-power hungry, very high clock, share instruction cache and FlexFPU between two cores in the module, first consumer octa-core processor, CMT (Clustered Multi-Thread), FMA, OpenCL, support up to 64 socket per chipset. |
2011 | AMD APU C, E and Z Series (Bobcat) | 64 | — | 36 | Out-of-order, 64-bit (integer CPU), on-die GPU; low power (Bobcat), Socket FM1 (Desktop) |
2011 | AMD APU A and E Series (Llano) | 64 | — | 40 | on-die GPU, first generation fusion APU |
2011 | AMD APU A Series (Bulldozer, Trinity and later) | 64 | — | 48 | SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU, Socket FM2 or Socket FM2+, GPGPU |
2011 | 2nd and 3rd gen. Intel Core i3, i5 and i7 (Sandy Bridge and Ivy Bridge) | 64 | — | 42 | Internal Ring connection, Intel Turbo Boost 2.0, F16C[5] AVX, GPGPU, Micro-operation cache(Uop Cache), relatively long pipeline (14 to 19 stages),[6]LGA 1155 socket. |
2012 | Intel Xeon Phi (Larrabee) | 64 | — | 36 | many integrated core (MIC) architecture (w/62), in-order P54C with x86-64, very wide vector unit, LRBni instructions (8× 64-bit), four threads per core. |
2013 | 4th and 5th gen. Intel Core i3, Core i5 and Core i7 (Haswell and Broadwell) | 64 | — | 44 | AVX2, FMA3, TSX, BMI1, BMI2 and ABM instructions, Intel ADX, Fully integrated voltage regulator (FIVR), Intel Turbo Boost 3.0 Max(Broadwell-E), high clock rate, LGA 1150 or LGA 2011 socket |
2015 | 6th, 7th and 8th gen. Intel Core i3, i5, i7 and i9 (Skylake, Kaby Lake and Coffee Lake) | 64 | — | 46 | Out-of-order, 64-bit (integer CPU), AVX-512, Intel SGX, Intel MPX, high clock rate, integrated on-die southbridge, integrated on-die x86 MIC array GPU, SoC, MIC, LGA 1151 socket. |
2017 | AMD Ryzen 3, Ryzen 5, Ryzen 7 and Ryzen Threadripper (Zen and Zen+) | 64 | — | 48 | Multiple CCXs connected through infinity Fabric[7], eXtended Frequency Range (XFR)[8], SenseMI, Simultaneous Multi Threading (SMT)[9], AM4/TR4 Socket |
First introduced | Prominent CPU brands | Linear address size (bits) | Segment / offset size (bits) | Physical address size (bits) | Notable (new) features |
- ^ Cite error: The named reference
Athlon PAE
was invoked but never defined (see the help page). - ^ "Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet" (PDF). Intel. June 2009. p. 66.
- ^ "Dual-Core Intel Xeon Processor 5100 Series Datasheet" (PDF). Intel. August 2007. p. 24.
- ^ "Intel Xeon Processor 7200 Series and 7300 Series Datasheet" (PDF). Intel. September 2008. p. 87.
- ^ Chuck Walbourn (September 11, 2012). "DirectXMath: F16C and FMA". Games for Windows and the DirectX SDK blog. Microsoft.
- ^ Anand Lal Shimpi (October 5, 2012). "Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel". Anandtech. The Haswell Front End.
- ^ Cutress, Ian. "The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700". Retrieved 2018-03-24.
- ^ Verry, Tim (4 March 2017). "PSA: AMD XFR Enabled On All Ryzen CPUs, X SKUs Have Wider Range | PC Perspective". www.pcper.com. Retrieved 2018-03-24.
{{cite web}}
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(help) - ^ Cutress, Ian. "The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700". Retrieved 2018-03-24.
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