SPARC T3

SPARC T3

SPARC T3 Micrograph
General information
Launched	2010
Marketed by	Oracle Corporation
Designed by	Sun Microsystems
Performance
Max. CPU clock rate	1.67 GHz
Architecture and classification
Instruction set	SPARC V9
Physical specifications
Cores	16

The SPARC T3 microprocessor (previously known as UltraSPARC T3, codenamed Rainbow Falls, and also known as UltraSPARC KT or Niagara-3 during development) is a multithreading, multi-core CPU produced by Oracle Corporation (previously Sun Microsystems). Officially launched on 20 September 2010, it is a member of the SPARC family, and the successor to the UltraSPARC T2.

History

SPARC T3 Processor

An online IT publication, The Register incorrectly reported in June 2008 that the microprocessor will have 16 cores, each with 16 threads, but published a roadmap in September 2009 showing 8 threads per core. During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads. According to the ISSCC 2010 presentation:

"A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s support the required bandwidth. Six clock and four voltage domains, as well as power management and circuit techniques, optimize performance, power, variability and yield trade-offs across the 377mm² die."

Support for the UltraSPARC T3 was confirmed on July 16th 2010 when the ARCBot under Twitter noted unpublished PSARC/2010/274 which revealed a new "-xtarget value for UltraSPARC T3" being included in OpenSolaris. The later launch of the product did not retain the "Ultra" portion of the name in marketing literature, however.

During Oracle Openworld in San Francisco on September 20, 2010, the processor was officially launched as the "SPARC T3" accompanied by new systems and new performance benchmarks claiming world-record performance in marketing literature. Varied real-world application benchmarks were released with full system disclosures. Internationally recognized SPEC benchmarks were also released with full system disclosures. Oracle disclosed that SPARC T3 was built with a 40 nm process.

Features

T3 Die Micrograph

• 16 CPU Cores
• 8 Hardware Threads per Core
• 6 MB Level 2 Cache
• 2 Embedded Coherency Controllers
• 6 Coherence Links
• 14 unidirectional lanes per Coherence Link
• SMP to 4 sockets without glue circuitry
• 4 DDR3 Memory Channels
• Embedded PCIe I/O Interfaces
• 16 Embedded Crypto Acceleration Engines
• 2 Embedded 1GigE/10GigE Interfaces
• 2.4Tb/s aggregate throughput per socket

Systems

Oracle's release of their T3 server line refreshed fewer physical products from the former T2 and T2+ server lines, reducing the total number of servers respectively to 4. The new server line includes:

• One Socket SPARC T3-1 2U Rack Server
• One Socket SPARC T3-1B Blade Server
• Two Socket SPARC T3-2 Server
• Four Socket SPARC T3-4 Server

Virtualization

Like the prior T1, T2, and T2+ processors, the T3 supports Hyper-Privileged execution mode. The T3 supports up to 128 Logical Domains or Oracle VM Server for SPARC.

Performance Improvement versus T2 and T2+

The SPARC T3 processor is effectively two T2+ processors on a single die. The T3 has:

• Double the cores (16) of a T2 or T2+
• Double the 10Gig ethernet ports (2) over a T2+
• Double the crypto accelerator cores (16) over a T2 or T2+
• Crypto engines support more algorithms than the T2 or T2+ including: DES, 3DES, AES, RC4, SHA1, SHA256/384/512, Kasumi, Galois Field, MD5, RSA to 2048 key, ECC, CRC32
• Over 1.9x Cryptography Performance Throughput Increase
• Faster DDR3 RAM interface over the T2 or T2+ DDR2 interface
• Double the throughput
• Double the memory capacity
• Quadruple the I/O throughput
• Two PCIe 2.0 eight lane interfaces vs one PCIe former generation eight lane interface

See also

• UltraSPARC T1 – The predecessor to T2, also Sun's first multicore and multithread CPU
• UltraSPARC T2 – The predecessor to T3