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This is an old revision of this page, as edited by CopperQA (talk | contribs) at 01:09, 19 September 2015 (→‎Semi-protected edit request on 18 September 2015). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

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8088 should be in the lede.

The lede should mention the 8088, given that it mentions the 8080, and the topic is x86. and why is this article locked? 68.173.49.156 (talk) 22:20, 12 February 2015 (UTC)[reply]

I added a brief mention of the 8088. It's locked because of "persistent sock-puppetry"; this edit protected it. Guy Harris (talk) 22:57, 12 February 2015 (UTC)[reply]

Itanium

50-bits of physical memory addressing and 64-bits of virtual addressing

from itanium-9000-9100-datasheet.pdf and itanium-9300-9500-datasheet.pdf, useful or not. 119.51.184.193 (talk) 00:30, 15 February 2015 (UTC)[reply]

Perhaps useful on the Itanium page or the Montecito (processor) and Tukwila (processor) pages; not relevant to the very-definitely-non-IA-64/Itanium x86 instruction set so not useful on this page. Guy Harris (talk) 01:12, 15 February 2015 (UTC)[reply]
OK, this is another sock puppet of Janagewen, I am fighting for the fair and freedom of Wikipedia.org all the time for ever, OK, but is the information of that table relating with Itanium correct or not? 221.9.23.11 (talk) 01:18, 15 February 2015 (UTC)[reply]
It might depend on the chip and, in any case, unlike the Atom chips (which are standard x86 chips) and the Transmeta chips (which aren't supposed to run anything other than the Code Morphing Software and code that the CMS has translated natively; the operating system and application code that's run on it is IA-32 code). those Itanium chips that ran IA-32 code in hardware ran it as a compatibility mode, similar to PDP-11 compatibility mode on some VAXes, so the addressing limits for the IA-64/Itanium instruction set are completely irrelevant to its IA-32 engine, and don't belong here. Guy Harris (talk) 01:46, 15 February 2015 (UTC)[reply]
OK, I would wait till 15 April 2015 to blank the relate information on that table. — Preceding unsigned comment added by 221.9.23.11 (talk) 02:21, 15 February 2015 (UTC)[reply]

regarding protected mode

according to computer experts i talked to during the 90s protected mode was not available on the 80286. it was first available on the 80386. 84.213.45.196 (talk) 16:15, 9 July 2015 (UTC)[reply]

You presumably mean "experts", in quotes, as no actual expert, i.e. no actual knowledgable person, would say that. The 80286 most definitely did have protected mode - the reference for that on the protected mode page is:
  • "2.1.2 The Intel 286 Processor (1982)". Intel 64 and IA-32 Architectures Software Developer's Manual. Denver, Colorado: Intel. May 2007. p. 34.
What the 80286 didn't have was support for demand paging; it didn't divide any address space into fixed-length pages, each of which can be present in memory or absent.
It may not have been used as much on the 286 by the main operating systems for x86 processors, but there were definitely operating systems for the 286 that did use it, such as various UNIX ports and OS/2. Guy Harris (talk) 17:44, 9 July 2015 (UTC)[reply]
i tried to run games requiring protected mode on a 80286 and they would not work because it did not have protected mode. it could however run any super vga requiring game that did not require protected mode.84.213.45.196 (talk) 20:49, 9 July 2015 (UTC)[reply]
No, they didn't work because the 286 didn't have the right type of protected mode for the software you were trying to run. As the protected mode article says in the section on the 286:
The initial protected mode, released with the 286, was not widely used.[1] It was used for example by Microsoft Xenix (around 1984),[2] by Coherent,[3] and by Minix.[4] Several shortcomings such as the inability to access the BIOS or DOS calls due to inability to switch back to real mode without resetting the processor prevented widespread usage.[5] Acceptance was additionally hampered by the fact that the 286 only allowed memory access in 16 bit segments via each of four segment registers, meaning only 4*216 bytes, equivalent to 256 kilobytes, could be accessed at a time.[1] Because changing a segment register in protected mode caused a 6-byte segment descriptor to be loaded into the CPU from memory, the segment register load instruction took many tens of processor cycles, making it much slower than on the 8086; therefore, the strategy of computing segment addresses on-the-fly in order to access data structures larger than 128 kilobytes (the combined size of the two data segments) became impractical, even for those few programmers who had mastered it on the 8086/8088.

References

  1. ^ a b Kaplan, Yariv (1997). "Introduction to Protected-Mode" (Article). Internals.com. Retrieved 2007-07-24.
  2. ^ http://www.tenox.net/docs/microsoft_xenix_30_286_press_release.pdf
  3. ^ http://textfiles.com/internet/FAQ/coherent.faq
  4. ^ http://minix.net/minix/minix.html
  5. ^ Mueller, Scott (March 24, 2006). "P2 (286) Second-Generation Processors". Upgrading and Repairing PCs, 17th Edition (Book) (17 ed.). Que. ISBN 0-7897-3404-4. Retrieved July 2007. {{cite book}}: Check date values in: |accessdate= (help); External link in |chapterurl= (help); Unknown parameter |chapterurl= ignored (|chapter-url= suggested) (help)
and the section on the 386 indicates that the 80386 fixed several of those issues - it offered a larger flat address space and made it easier to return to real mode from protected mode.
So your games that "required protected mode" really required the IA-32 version of protected mode, not just protected mode. Guy Harris (talk) 21:14, 9 July 2015 (UTC)[reply]

Semi-protected edit request on 18 September 2015

Generation First introduced Prominent consumer CPU brands Linear/physical address space Notable (new) features
1st 1978 Intel 8086, Intel 8088 and clones 16-bit / 20-bit First x86 microprocessors
1982 Intel 80186, Intel 80188 and clones, NEC V20/V30 Hardware for fast address calculations, fast multiplication and division
2nd Intel 80286 and clones 16-bit ((14+16)-bit segmented) / 24-bit MMU, for protected mode and a larger address space
3rd (IA-32) 1985 Intel 80386 and clones, AMD Am386 32-bit ((14+32)-bit segmented) / 32-bit 32-bit instruction set, MMU with paging, PGA132 socket
3rd/4th 1992 Cyrix Cx486SLC, Cyrix Cx486DLC L1 cache and pipelining introduced into the 386 platform, PGA132 socket
4th (FPU) 1989 Intel 80486 and clones, AMD Am486 RISC-like pipelining, integrated x87 FPU (80-bit), on-chip cache, PGA168 socket
4th/5th 1997 Am5x86, Cyrix 5x86, Pentium OverDrive Partial Pentium's specification brought into the 486 platform
5th 1993 Pentium, Pentium MMX
Rise mP6		 Superscalar 64-bit databus, faster FPU, MMX (2× 32-bit), 2-way coherence SMP (Pentium), Socket 7
5th/6th 1996 AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III-Samuel (2000), VIA C3-Samuel2 / VIA C3-Ezra (2001) Discrete microarchitecture (µ-op translation)
6th 1995 Pentium Pro 32-bit ((14+32)-bit segmented) / 36-bit physical (PAE) µ-op translation, conditional move instructions, Out-of-order register renaming, speculative execution, PAE, full speed on-chip L2 cache, 4-way no coherence SMP, Socket 8
1997 Pentium II, Pentium III (1999), Celeron (1998), Xeon (1998) SSE (2× 64-bit) (Pentium III), half speed on-package L2 cache (Pentium II/Pentium III Katmai), full speed on-die L2 Cache (Mendocino, Coppermine), SLOT 1 or Socket 370
1997 AMD K6/2/III, Cyrix III-Joshua (2000) 32-bit ((14+32)-bit segmented) / 32-bit On-die L2-Cache (K6-III, Cyrix III Joshua), 3DNow!, no PAE support, Super Socket 7 (K6-2)
6th/7th 2003 Pentium M, Intel Core (2006), Pentium Dual Core (2007)
VIA C7 (2005)		 32-bit ((14+32)-bit segmented) / 36-bit physical (PAE) Optimized for low thermal design power, four pumped FSB
7th 1999 Athlon
Athlon XP/MP (2001), Duron (2000), Sempron (2004)		 Superscalar FPU, wide design (up to three x86 instr./clock), divided speed on-package L2 cache (Classic) or full speed on-die L2 cache, 2-way x-bar based SMP (XP/MP), Slot A (Classic) or Socket A
2000 Pentium 4
Pentium 4 HT (2003), Celeron (2002), Celeron D (2004)		 Deeply pipelined, high frequency, SSE2, SSE3 (Prescott), HT (Northwood), Socket 478
8th (x86-64) 2003 Athlon 64, Athlon 64 FX, Opteron
Athlon 64 X2 (2005), Sempron (2004), Sempron X2 (2008)		 64-bit / 40-bit physical AMD64 processor (excluding 32-bit Sempron), on-die memory controller, HyperTransport, CMP, virtualisation (AMD-V) on some models, Socket 754/939/940 or AM2 socket
7th/8th 2004 Pentium 4 HT F Series
Pentium 4 506/516/517/519K/524/5x1/6xx (2005)
Celeron D 3x1/3x6/355 (2005)
Pentium D (2005)		 64-bit / 36-bit physical EM64T technology introduced, even deeper pipelined, very high frequency, CMP, virtualisation (6x2/9x0), LGA 775 socket
8th 2006 Intel Core 2
Pentium Dual Core (2007)
Celeron (2007), Celeron Dual Core (2008)		 64-bit / 36-bit physical Intel 64 processor, low power, multi-core, lower clock frequency, SSE4 (Penryn), wide dynamic execution, µ-op fusion, macro-µ-op fusion, virtualisation (Intel VT) on some models
2007 AMD Phenom, AMD Phenom II (2008), Athlon II (2009) 64-bit / 48-bit physical Monolithic quad-core, SSE4a, HyperTransport 3, AM2+ or AM3 socket
2008 VIA Nano 64-bit / 36-bit physical Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption; very low power; adaptive power management
8th/9th 2008 Intel Core i7, Core i5 (2009) (Nehalem/Westmere)
Core i3 (2010), Pentium (2010), Celeron (2010) (Westmere)		 64-bit / 36-bit physical QuickPath, native memory controller, on-die L3 cache, modular, Intel HD Graphics introduced onto CPU chip (Clarkdale), LGA 1366 (Nehalem) or LGA 1156 socket
Intel Atom In-order but highly pipelined, very-low-power, some models (Diamondville) with 32-bit (integer CPU), on-die GPU (Penwell, Cedarview)
2011 AMD APU C, E and Z Series (Bobcat) Out-of-order, 64-bit (integer CPU), on-die GPU; low power (Bobcat), Socket FM1 (Desktop)
AMD APU A and E Series (Llano) 64-bit / 48-bit physical
9th (GPGPU) 2011 AMD APU A Series (Bulldozer, Trinity and later) SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU, Socket FM2 or Socket FM2+
Intel Core i3/i5/i7 (Sandy Bridge/Ivy Bridge) 64-bit / 40-bit physical Internal Ring connection, GPGPU, LGA 1155 socket
2013 Intel Core i3/i5/i7 (Haswell/Broadwell) 64-bit / 44-bit physical AVX2, FMA3, TSX, BMI1, and BMI2 instructions, LGA 1150 socket
10th (SoC, MIC) 2015/2016 Intel Core i3/i5/i7 (Skylake/Kaby Lake/Cannonlake) Out-of-order, 64-bit (integer CPU), AVX3, integrated on-die southbridge, integrated on-die x86 MIC array GPU, LGA 1151 socket
Others 2000 Transmeta Crusoe, Transmeta Efficeon 32-bit ((14+32)-bit segmented) / 32-bit VLIW design with x86 emulator, on-die memory controller
2001 Intel Itanium IA-32 compatibility mode 32-bit ((14+32)-bit segmented) / N/A EPIC architecture with an on-package engine (pre-2006 chips, later using IA-32 Execution Layer) that provides backward support for most IA-32 applications
2012 Intel Xeon Phi (Larrabee) (MIC pilot) Many Integrated Cores (62), In-order P54C with x86-64, very wide vector unit, LRBni instructions (8× 64-bit)

CopperQA (talk) 04:51, 18 September 2015 (UTC)[reply]

 Not done - This is not a "spot the difference competition"
If you want to suggest a change, please request this in the form "Please replace XXX with YYY" or "Please add ZZZ between PPP and QQQ".
Please also cite reliable sources to back up your request, without which no information should be added to, or changed in, any article. - Arjayay (talk) 09:24, 18 September 2015 (UTC)[reply]
OK, enough response. CopperQA (talk) 09:40, 18 September 2015 (UTC)[reply]
I re-brought this table because it is readable and reliable, worth something to read. Common readers could differentiate each generation of processors much more easily, at least they could easy figure out which processor for which socket. For computer science students, they could find a hint to customise their low cost or phase-out multi-processor based machine for system level programming. This table could make the main article worth more than an instruction but a useful guide. Reliable source? I believe the readers from all over the world is the best reliable source, they could correct and even extend this table too. Let us dip into the history of the main article, who is really making useful contributions? And who is always stop those useful contributions to appear for some unknown reasons? I always believe Wikipedia is a fair place, and everyone is equal. For all those stoppers and rollbackers, I would always say no! CopperQA (talk) 11:18, 18 September 2015 (UTC)[reply]

Note: In the above table, AMD FX processor is missing! I consider where to put it for a long time, but should I sort on the 8th, 8th/9th or 9th generation? Frankly, there is not too many differences between Athlon 64 and AMD FX, just one ISA two different implementation at the same tech level. Socket AM1 and Intel Bay Trail processors might be sorted into the 9th/10th generation in the future, they gain success on personal consumer market. CopperQA (talk) 01:09, 19 September 2015 (UTC)[reply]

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