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ARM Cortex-A15

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ARM Cortex-A15
General information
LaunchedIn production late 2011,[1] to market late 2012[2]
Designed byARM Holdings
Performance
Max. CPU clock rate1.0 GHz  to 2.5 GHz 
Cache
L1 cache64 KB (32 KB I-cache, 32 KB D-cache) per core
L2 cacheUp to 4 MB[3] per cluster
L3 cachenone
Architecture and classification
Technology node32 nm/28 nm initially[4] to 22 nm roadmap[4]
MicroarchitectureARMv7-A
Physical specifications
Cores
  • 1–4 per cluster, 1–2 clusters per physical chip[5]

The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz.[6]

Overview

Main article: Comparison of ARMv7-A cores

ARM has claimed that the Cortex-A15 core is 40 percent more powerful than the Cortex-A9 core with the same number of cores at the same speed.[7] The first A15 designs came out in the autumn of 2011, but products based on the chip did not reach the market until 2012.[1]

Key features of the Cortex-A15 core are:

  • 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.[8][9] As per the x86 Physical Address Extension, virtual address space remains 32 bit.[10]
  • 15 stage integer/17–25 stage floating point pipeline, with out-of-order speculative issue 3-way superscalar execution pipeline[11]
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (CCI-400, an AMBA-4 coherent interconnect) and 4 clusters per chip with CCN-504.[12] ARM provides specifications but the licensees individually design ARM chips, and AMBA-4 scales beyond 2 clusters. The theoretical limit is 16 clusters; 4 bits are used to code the CLUSTERID number in the CP15 register (bits 8 to 11).[13]
  • DSP and NEON SIMD extensions onboard (per core)
  • VFPv4 Floating Point Unit onboard (per core)
  • Hardware virtualization support
  • Thumb-2 instruction set encoding to reduce the size of programs with little impact on performance
  • TrustZone security extensions
  • Jazelle RCT for JIT compilation
  • Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
  • 32 KB data + 32 KB instruction L1 cache per core
  • Integrated low-latency level-2 cache controller, up to 4 MB per cluster

Chips

First implementation came from Samsung in 2012 with the Exynos 5 Dual, which shipped in October 2012 with the Samsung Chromebook Series 3 (ARM version), followed in November by the Google Nexus 10.

Press announcements of current implementations:

Other licensees, such as LG,[22][23] are expected to produce an A15 based design at some point.

Systems on a chip

Model Number Semiconductor technology CPU GPU Memory interface Wireless radio technologies Availability Utilizing devices
HiSilicon K3V3 28 nm HPL big.LITTLE architecture using
1.8 GHz dual-core ARM Cortex-A15
+ dual-core ARM Cortex-A7 		Mali-T628 H2 2014
Nvidia Tegra 4 T40 28 nm HPL 1.9 GHz quad-core ARM Cortex-A15[24] + 1 low power core Nvidia GeForce @ 72 core, 672 MHz, 96.8 GFLOPS = 48 PS + 24 VU × 0.672 × 2 (96.8 GFLOPS)[25](support DirectX 11+, OpenGL 4.X, and PhysX) 32-bit dual-channel DDR3L or LPDDR3 up to 933 MHz (1866 MT/s data rate)[24] Category 3 (100 Mbit/s) LTE Q2 2013 Nvidia Shield Tegra Note 7
Nvidia Tegra 4 AP40 28 nm HPL 1.2-1.8 GHz quad-core + low power core Nvidia GPU 60 [24] cores (support DirectX 11+, OpenGL 4.X, and PhysX) 32-bit dual-channel 800 MHz LPDDR3 Category 3 (100 Mbit/s) LTE Q3 2013
Nvidia Tegra K1 28 nm HPm 2.3 GHz quad-core + battery saver core Kepler SMX (192 CUDA cores, 8 TMUs, 4 ROPs) 32-bit dual-channel DDR3L, LPDDR3 or LPDDR2 Q2 2014 Jetson TK1 development board,[26] Lenovo ThinkVision 28, Xiaomi MiPad, Shield Tablet
Texas Instruments OMAP5430 28 nm 1.7 GHz dual-core PowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator 32-bit dual-channel 532 MHz LPDDR2 Q2 2013 phyCore-OMAP5430[27]
Texas Instruments OMAP5432 28 nm 1.5 GHz dual-core PowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator 32-bit dual-channel 532 MHz DDR3 Q2 2013 DragonBox Pyra, SVTronics EVM,[28] Compulab SBC-T54[29]
Texas Instruments AM57x 28 nm 1.5 GHz single or dual-core PowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator 32-bit dual-channel 532 MHz DDR3 Q4 2015 BeagleBoard-X15, Elesar Titanium[30]
Texas Instruments 66AK2x 28 nm 1.5 GHz single, dual, and quad core devices 1-8 C66x DSP cores, radio acceleration, and many other application specific accelerators Q4 2015
Exynos 5 Dual[31]
(previously Exynos 5250)[32] 		32 nm HKMG 1.7 GHz dual-core ARM Cortex-A15 ARM Mali-T604[33] (quad-core) @ 533 MHz; 68.224 GFLOPS [citation needed] 32-bit dual-channel 800 MHz LPDDR3/DDR3 (12.8 GB/sec) or 533 MHz LPDDR2 (8.5 GB/sec) Q3 2012[32] Samsung Chromebook XE303C12,[34] Google Nexus 10, Arndale Board,[35] Huins ACHRO 5250 Exynos,[36] Freelander PD800 HD,[37] Voyo A15, HP Chromebook 11, Samsung Homesync
Exynos 5 Octa[38][39][40]
(internally Exynos 5410) 		28 nm HKMG 1.6 GHz[41] quad-core ARM Cortex-A15 and 1.2 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE)[42] IT PowerVR SGX544MP3 (tri-core) @ 480 MHz 49 GFLOPS (532 MHz in some full-screen apps)[43] 32-bit dual-channel 800 MHz LPDDR3 (12.8 GB/sec) Q2 2013 Samsung Galaxy S4 I9500,[44][45] Hardkernel ODROID-XU,[46] Meizu MX3, ZTE Grand S II TD[47] ODROID-XU
Exynos 5 Octa[48]
(internally Exynos 5420) 		28 nm HKMG 1.8-1.9 GHz quad-core ARM Cortex-A15 and 1.3 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) ARM Mali-T628 MP6 @ 533 MHz; 109 GFLOPS 32-bit dual-channel 933 MHz LPDDR3e (14.9 GB/sec) Q3 2013 Samsung Chromebook 2 11.6",[49] Samsung Galaxy Note 3,[50] Samsung Galaxy Note 10.1 (2014 Edition), Samsung Galaxy Note Pro 12.2, Samsung Galaxy Tab Pro (12.2 & 10.1), Arndale Octa Board, Galaxy S5 SM-G900H [51]
Exynos 5 Octa[52]
(internally Exynos 5422) 		28 nm HKMG 2.1 GHz quad-core ARM Cortex-A15 and 1.5 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) ARM Mali-T628 MP6 @ 695 MHz (142 Gflops) 32-bit dual-channel 933 MHz LPDDR3/DDR3 (14.9 GB/sec) Q2 2014 Galaxy S5 SM-G900, Hardkernel ODROID-XU3 & ODROID-XU4[53]
Exynos 5 Octa[54]
(internally Exynos 5800) 		28 nm HKMG 2.1 GHz quad-core ARM Cortex-A15 and 1.3 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) ARM Mali-T628 MP6 @ 695 MHz (142 Gflops) 32-bit dual-channel 933 MHz LPDDR3/DDR3 (14.9 GB/sec) Q2 2014 Samsung Chromebook 2 13,3"[55]
Exynos 5 Hexa[56]
(internally Exynos 5260) 		28 nm HKMG 1.7 GHz dual-core ARM Cortex-A15 and 1.3 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) ARM Mali-T624 32-bit dual-channel 800 MHz LPDDR3 (12.8 GB/sec) Q2 2014 Galaxy Note 3 Neo (announced January 31, 2014), Samsung Galaxy K zoom[57]
Allwinner A80 Octa[58] 28 nm HPm Quad-core ARM Cortex-A15 and Quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) PowerVR G6230 (Rogue) 32-bit dual-channel DDR3/DDR3L/LPDDR3 or LPDDR2[59]

See also

References

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  2. ^ ARM Expects First Cortex-A15 Devices in Late 2012
  3. ^ Cortex-A15 Processor — Product description
  4. ^ a b ARM Unveils Cortex-A15 MPCore Processor to Dramatically Accelerate Capabilities of Mobile, Consumer and Infrastructure Applications — in the Supporting Technology section
  5. ^ "CoreLink Network Interconnect for AMBA AXI". Archived from the original on 2011-04-05. Retrieved 2011-05-22.
  6. ^ ARM Cortex-A15 - ARM Processor
  7. ^ Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9
  8. ^ ARM7 40-bit, virtualization
  9. ^ ARM e-mail to LINUX: Add support for the Large Physical Address Extensions
  10. ^ "Calxeda plots server dominance with ARM SoCs."
  11. ^ Exploring the Design of the Cortex-A15 Processor Archived 2013-11-12 at the Wayback Machine Travis Lanier
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  13. ^ "Cortex-A15 MPCore Technical Reference Manual"
  14. ^ Broadcom announces plans for ARM's Cortex-A15 SoC | thinq
  15. ^ Huawei Announces HiSilicon K3V3 Chipset For Smartphones on Tom's Hardware
  16. ^ NVIDIA Announces "Project Denver" to Build Custom CPU Cores Based on ARM Architecture, Targeting Personal Computers to Supercomputers - NVIDIA Newsroom
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