Comparison of ARMv8-A cores

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This is a table of 64/32-bit ARMv8-A architecture cores; comparing microarchitectures which implement the AArch64 instruction set and mandatory or optional extensions of it. All chips of this type have a floating-point unit (FPU) that is better than in older ARMv7 and NEON (SIMD). Some chips have coprocessors, such as AppliedMicro Helix that also includes cores from the older 32-bit architecture (ARMv7). Some chips (SoC) can combine both ARM Cortex-A53 and ARM Cortex-A57 as Samsung Exynos 7 Octa.

Table[edit]

Core Decode Pipeline depth Out-of-order execution Branch prediction big.LITTLE role Execution ports Process technology
(in nm)
L0 cache L1 cache
I.cache+D.cache
(in KiB)
L2 cache L3 cache Core configurations DMIPS/MHz
ARM Cortex-A53 3-wide 8 stages No ? LITTLE 2 28 / 20 ? 8–64 + 8–64 128 KiB–2 MiB ? 1–4+ 2.3
ARM Cortex-A57 3-wide 15+ Yes Two-level big 8 28 / 20 ? 48 + 32 0.5–2 MiB ? 1–4+ 4.1 to 4.76
Apple Cyclone[1] 6‑wide[2] ? Yes[2] ? No 9[2] 28[3] / 20 ? 64 + 64[2] 1 MiB[2] 4 MiB[2] 2,[4] 3 (in A8X) ?
Nvidia Denver[5] 7-wide
"concurrent micro-ops"
? Yes
"Dynamic Code Optimization"
? No 7 28 ? 128 + 64 2 MiB ? 2 ?
Cavium ThunderX ? ? ? ? ? ? 28 ? ? ? ? 8–16, 24–48 ?
AppliedMicro X-Gene 4-wide XGene 1 ? Yes - XGene 2 (in-order on older) "100 instructions in flight in processor module" ? ? ? X-Gene 1 "Storm" 40 nm;
X-Gene 2 "Shadowcast" 28 nm 16-core 2.8 GHz (sampling);
X-Gene 3 "Skylark" 16 nm FINFET (in design)[6]
? Yes Yes XGene 1 - 8 MB "hangs off of this coherent network";
XGene 2 - 2400 KiB combined in hierarchy (>2400 next version)
8 ("module has a pair of cores") @ 2.4 GHz - XGene 1 (in production);
16 - X-Gene 2 (sampling);
64 - XGene 3 (2015)
?
AppliedMicro Helix ? ? ? ? ? ? 28 / 40 ? 32 + 32 (per core; write-trough w/parity)[7] 256 KiB shared per core pair (with ECC) 2, 4 or 8 MB shared 4 or 8 ARMv8 (28 nm) @ up to 2.4 GHz
or 2 or 4 ARMv8 @ up to 2.0 GHz;
256 KiB or 1 MB "On-Chip Memory" in addition to cache; plus optionally 4× Cortex-A5 at 500 MHz
?
Broadcom Vulcan 8-wide "4 uops"[8][9] "quad-threaded" ? ? Multi-level ? ? 16 (FINFET)[10] ? 32 + 32 (data 8-way) 256 KiB (8-way) ? 3 GHz ?

References[edit]

  1. ^ Lal Shimpi, Anand (September 17, 2013). "The iPhone 5s Review: The Move to 64-bit". AnandTech. Retrieved July 3, 2014. 
  2. ^ a b c d e f Lal Shimpi, Anand (March 31, 2014). "Apple's Cyclone Microarchitecture Detailed". AnandTech. Retrieved July 3, 2014. 
  3. ^ Dixon-Warren, Sinjin (January 20, 2014). "Samsung 28nm HKMG Inside the Apple A7". Chipworks. Retrieved July 3, 2014. 
  4. ^ Lal Shimpi, Anand (September 17, 2013). "The iPhone 5s Review: A7 SoC Explained". AnandTech. Retrieved July 3, 2014. 
  5. ^ Stam, Nick (August 11, 2014). "Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android". NVidia. Retrieved August 11, 2014. 
  6. ^ Morgan, Timothy Prickett (August 12, 2014). "Applied Micro Plots Out X-Gene ARM Server Future". Enterprisetech. Retrieved October 9, 2014. 
  7. ^ Ganesh T S (October 3, 2014). "ARMv8 Goes Embedded with Applied Micro's HeliX SoCs". AnandTech. Retrieved October 9, 2014. 
  8. ^ https://hpcuserforum.com/presentations/santafe2014/Broadcom%20Monday%20night.pdf
  9. ^ http://www.linleygroup.com/events/agenda.php?num=24&day=1
  10. ^ "Broadcom Announces Server-Class ARMv8-A Multi-Core Processor Architecture". Broadcom. October 15, 2013. Retrieved August 11, 2014.