Intel MPX

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Intel MPX (Memory Protection Extensions) is a set of extensions to the x86 instruction set architecture. With compiler, runtime library and operating system support, Intel MPX brings increased security to software by checking pointer references whose normal compile-time intentions are maliciously exploited at runtime due to buffer overflows. Intel MPX will introduce new registers, and new instruction set extensions that operate on these registers.[1][2][3][4]

Intel MPX will be introduced as part of the Skylake microarchitecture.[5]

Overview[edit]

MPX uses four new 128-bit bounds registers, BND0 to BND3, each storing a pair of 64-bit lower bound (LB) and upper bound (UB) values of a buffer. The upper bound can be stored in ones' complement form, with the load instructions BNDMK and BNDCU performing the conversion. The architecture includes user-mode configuration register BNDCFGU, supervisor-mode configuration register IA32_BNDCFGS (a model-specific register), and status register BNDSTATUS, which provides memory address and error code in case of an exception.[6]

The application can use the Bounds Directory (BD) of several Bounds Tables (BT), which contain linear address pointer of a buffer along with its bounds. Two extended load/store instructions BNDLDX and BNDSTX will sync BNDx registers with the Bounds Directory, performing translation as necessary.[6]

See also[edit]

  • grsecurity – a set of security patches for the Linux kernel
  • PaX – a Linux kernel patch implementing least privilege protections for memory pages

References[edit]

External links[edit]