Power ISA
| Designer | |
|---|---|
| Bits | 32-bit/64-bit (32 → 64) |
| Introduced | 2006 |
| Version | 3.1 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed/Variable |
| Branching | Condition code |
| Endianness | Big/Bi |
| Extensions | AltiVec, APU, DSP, CBEA |
| Open | Yes, and royalty free |
| Registers | |
| |
The Power ISA is an instruction set architecture (ISA) developed by the OpenPOWER Foundation, led by IBM. It was originally developed by the now-defunct Power.org industry group.[citation needed] Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.
Power ISA is a RISC load/store architecture. It has multiple sets of registers:
- 32 × 32-bit or 64-bit general-purpose registers (GPRs) for integer operations.
- 64 × 128-bit vector scalar registers (VSRs) for vector operations and floating point operations.
- 32 × 64-bit floating-point registers (FPRs) as part of the VSRs for floating point operations.
- 32 × 128-bit vector registers (VRs) as part of the VSRs for vector operations.
- 8 × 4-bit condition register fields (CRs) for comparison and control flow.
- 11 special registers of various sizes: Counter Register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).
Instructions have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.
Power ISA has support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. There is also support for both big and little-endian addressing with separate categories for moded and per-page endianness, as well as support for both 32-bit and 64-bit addressing.
Different modes of operation include user, supervisor and hypervisor.
Categories
- Base – Most of Book I and Book II
- Server – Book III-S
- Embedded – Book III-E
- Misc – floating point, vector, signal processing, cache locking, decimal floating point, etc.
Books
The Power ISA specification is divided into five parts, called "books":
- Book I – User Instruction Set Architecture covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
- Book II – Virtual Environment Architecture defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
- Book III – Operating Environment Architecture includes exceptions, interrupts, memory management, debug facilities and special control functions. It is divided into two parts.
- Book III-S – Defines the supervisor instructions used for general-purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA.
- Book III-E – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
- Book VLE – Variable Length Encoded Instruction Architecture defines alternative instructions and definitions from Books I–III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big-endian byte ordering.
Specifications
Power ISA v.2.03
The specification for Power ISA v.2.03[1] is based on the former PowerPC ISA v.2.02[2] in POWER5+ and the Book E[3] extension of the PowerPC specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
Compliant cores
Power ISA v.2.04
The specification for Power ISA v.2.04[4] was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the Book III-S part regarding virtualization, hypervisor functionality, logical partitioning and virtual page handling.
Compliant cores
- All cores that comply with previous versions of the Power ISA
- The PA6T core from P.A. Semi
- Titan from AMCC
Power ISA v.2.05
The specification for Power ISA v.2.05[5] was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to Book I and Book III-S, including significant enhancements such as decimal arithmetic (Category: Decimal Floating-Point in Book I) and server hypervisor improvements.
Compliant cores
- All cores that comply with previous versions of the Power ISA
- POWER6
- PowerPC 476
Power ISA v.2.06
The specification for Power ISA v.2.06[6] was released in February 2009, and revised in July 2010.[7] It is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and e500-mc core. One significant new feature is vector-scalar floating-point instructions (VSX).[8] Book III-E also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations.
The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features.[7][9]
Compliant cores
Power ISA v.2.07
The specification for Power ISA v.2.07[10] was released in May 2013. It is based on Power ISA v.2.06 and includes major enhancements to logical partition functionality, transactional memory, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities (VSX-2), along with AES[10]: 257 [11] and Galois Counter Mode (GCM), SHA-224, SHA-256,[10]: 258 SHA-384 and SHA-512[10]: 258 (SHA-2) cryptographic extensions and cyclic redundancy check (CRC) algorithms.[12]
The spec was revised in April 2015 to the Power ISA v.2.07 B spec.[13]
Compliant cores
Power ISA v.3.0
The specification for Power ISA v.3.0[14][15] was released in November 2015. It is the first to come out after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of workloads and removes the server and embedded categories while retaining backwards compatibility and adds support for VSX-3 instructions. New functions include 128-bit quad-precision floating-point operations, a random number generator, hardware-assisted garbage collection and hardware-enforced trusted computing.
The spec was revised in March 2017 to the Power ISA v.3.0 B spec.[16]
Compliant cores
Power ISA v.3.1
The specification for Power ISA v.3.1[18] was released in May 2020. Mainly giving support for new functionality introduced in POWER10, but also includes the notion of optionality to the PowerISA specification. Instructions can now be eight bytes long, "prefixed instructions", compared to the usual four byte "word instructions". A lot of new functionality to SIMD and VSX instructions are also added.
Compliant cores
See also
References
- ^ "Power ISA v.2.03". Power.org. 2006-09-29. Archived from the original on 2012-11-24. Retrieved 2010-10-20.
- ^ "PowerPC Architecture Book, Version 2.02". IBM. 2005-02-24. Archived from the original on 2007-10-18. Retrieved 2007-03-16.
- ^ "PowerPC Book E v.1.0" (PDF). IBM. 2002-05-07. Retrieved 2007-03-16.
- ^ "Power ISA Version 2.04" (PDF). Power.org. 2007-06-12. Archived from the original (PDF) on 2007-09-27. Retrieved 2007-06-14.
- ^ "Power ISA Version 2.05". Power.org. 2007-10-23. Archived from the original on 2012-11-24. Retrieved 2007-12-18.
- ^ "Power.org Debuts Specification Advances and New Services At Power Architecture Developer Conference" (Press release). Power.org. 2007-09-24. Archived from the original on 2007-10-12. Retrieved 2007-09-24.
- ^ a b "Power ISA Version 2.06 Revision B". Power.org. 2010-07-23. Archived from the original on 2012-11-24. Retrieved 2011-02-12.
- ^ "Workload acceleration with the IBM POWER vector-scalar architecture". IBM. 2016-03-01. Retrieved 2017-05-02.
- ^ "Power ISA 2.06 Rev. B enables full hardware virtualization for embedded space". EETimes. 2010-11-03. Retrieved 2011-06-08.
- ^ a b c d "Power ISA Version 2.07" (PDF). Power.org. 2013-05-15. Retrieved 2015-05-23.
- ^ Leonidas Barbosa (2014-09-21). "POWER8 in-core cryptography". IBM.
- ^ Performance Optimization and Tuning Techniques for IBM Power Systems Processors Including IBM POWER8. IBM. August 2015. p. 48. ISBN 9780738440927.
- ^ "Power ISA Version 2.07 B". Power.org. 2015-04-09. Retrieved 2017-01-06.
- ^ Announcing a New Era of Openness with Power 3.0
- ^ "Power ISA Version 3.0". openpowerfoundation.org. 2016-11-30. Retrieved 2017-01-06.
- ^ "Power ISA Version 3.0 B". Power.org. 2017-03-27. Retrieved 2019-08-11.
- ^ [PATCH, COMMITTED] Add full Power ISA 3.0 / POWER9 binutils support
- ^ "Power ISA Version 3.1". openpowerfoundation.org. 2020-05-01. Retrieved 2020-05-23.
- ^ Carlos Eduardo Seo (2020-05-12). "We released the Instruction Set Architecture for POWER10. Power ISA v3.1 is available at the IBM Portal for OpenPOWER". twitter.com. Retrieved 2020-05-23.