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Video Coding Engine

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Video Coding Engine[1] (VCE, sometimes incorrectly referred to as Video Codec Engine[2]) is AMD's video encoding ASIC implementing the video codec H.264/MPEG-4 AVC. Since 2012 it is integrated into all of their GPUs and APUs.

Video Coding Engine was introduced with the Radeon HD 7900 on 22 December 2011.[3][4][5] VCE occupies a considerable amount of the die surface and is not to be confused with AMD's Unified Video Decoder (UVD).

Overview

In "full-fixed mode" the entire computation is done by the fixed-function VCE unit. Full-fixed mode can be accessed through the OpenMAX IL API.
The entropy encoding block of the VCE ASIC is also separately accessible, enabling "hybrid mode". In "hybrid mode" most of the computation is done by the 3D engine of the GPU. Using AMD's Accelerated Parallel Programming SDK and OpenCL developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding.

The handling of video data involves computation of data compression algorithms and possibly of video processing algorithms. As the template Compression methods shows, lossy video compression algorithms involve the steps: Motion estimation (ME), Discrete cosine transform (DCT), and entropy encoding (EC).

AMD Video Codec Engine (VCE) is a full hardware implementation of the video codec H.264/MPEG-4 AVC. The ASIC is capable of delivering 1080p at 60 frames/sec. Because its entropy encoding block is also separately accessible Video Codec Engine can be operated in two modes: full-fixed mode and hybrid mode.[2][6]

By employing AMD APP SDK, available for Linux and Microsoft Windows, developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding. In hybrid mode, only the entropy encoding block of the VCE unit is used, while the remaining computation is offloaded to the 3D engine (GCN) of the GPU, so the computing scales with the number of available compute units (CUs).

VCE 1.0

As of April 2014, there are two versions of VCE.[1] Version 1.0 supports H.264 YUV420 (I & P frames), H.264 SVC Temporal Encode VCE, and Display Encode Mode (DEM).

It can be found on

  • Piledriver-based
    • Trinity APUs (Ax - 5xxx, e.g. A10-5800K)
    • Richland APUs (Ax - 6xxx, e.g. A10-6800K)
  • GPUs of the Southern-Island-Generation (GCN 1.0: CAYMAN, ARUBA (Trinity/Richland), CAPE VERDE, PITCAIRN, TAHITI, OLAND). These are
    • Radeon HD7700 series (HD 7790 (VCE 2.0))
    • Radeon HD7800 series
    • Radeon HD7900 series
    • Radeon HD8570 to 8990 (HD 8770 (VCE 2.0))
    • Radeon R5 240 / R7 240 / R7 250 / R7 250E / R7 250X / R7 265 / R9 270 / R9 270X / R9 280 / R9 280X
    • Radeon R5 330 / R5 340 / R7 340 / R7 350 / R7 370 / R9 370 / R9 370X
    • Mobile Radeon HD 77x0M to HD 7970M
    • Mobile Radeon HD 8000-Series
    • Mobile Radeon Rx M2xx Series (R9 M280X: VCE 2.0, R9 M295X: VCE 3.0)
    • Mobile Radeon R5 M330 to Radeon R9 M380 and Radeon R9 M390
    • FirePro Cards with 1st Generation GCN (GCN 1.0)

VCE 2.0

Compared to the first version, VCE 2.0 adds H.264 YUV444 (I-Frames), B-frames for H.264 YUV420, and improvements to the DEM (Display Encode Mode), which results in a better encoding quality.

It can be found on

  • Steamroller-based
    • Kaveri APUs (Ax - 7xxx, e.g. A10-7850K)
    • Godavari APUs (Ax - 7xxx e.g. A10-7890K)
  • Jaguar-based
    • Kabini APUs (e.g. Athlon 5350, Sempron 2650)
    • Temash APUs (e.g. A6-1450, A4-1200)
  • Puma-based
    • Beema and Mullins
  • GPUs of the Sea-Islands-Generation as well Bonaire or Hawaii GPUs (2nd generation Graphics Core Next GCN 1.1), such as
    • Radeon HD 7790 / HD 8770
    • Radeon R7 260 / R7 260X / R9 290 / R9 290X / R9 295X2
    • Radeon R7 360 / R9 360 / R9 390 / R9 390X
    • Mobile Radeon R9 M280X
    • Mobile Radeon R9 M385 / R9 M385X
    • Mobile Radeon R9 M470 / R9 M470X
    • FirePro-Cards with second Generation GCN 1.1

VCE 3.0

Video Coding Engine 3.0 (VCE 3.0) technology features a new high-quality video scaling.,[7] and will also support for High Efficiency Video Coding (HEVC, H.265,[8] but As of May 2015, there are no announcements about VP9 video codec support.[9][10][11]

It, together with UVD 6.0, can be found on 3rd generation of Graphics Core Next (GCN 1.2) with "Tonga", "Fiji", "Iceland", and "Carrizo" (VCE 3.1) based graphics controller hardware, which is now used AMD Radeon Rx 300 Series (Pirate Islands GPU family) and VCE 3.4 by actual AMD Radeon Rx 400 Series (Arctic Islands GPU family).

  • Tonga: Radeon R9 285, Radeon R9 380, Radeon R9 380X / Mobile Radeon R9 M390X / R9 M395 / R9 M395X / Radeon R9 M485X /
  • Tonga XT: FirePro W7100 / S7100X / S7150 / S7150 X2 /
  • Fiji: Radeon R9 Fury / R9 Fury X / R9 Nano / Radeon Pro Duo / FirePro S9300 / W7170M
  • Polaris: RX 460 / 470 / 480

Feature overview

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

[ VisualEditor ]
Platform High, standard and low power Low and ultra-low power
Codename Server Basic Toronto
Micro Kyoto
Desktop Performance Raphael Phoenix
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne
Entry
Basic Kabini Dalí
Mobile Performance Renoir Cezanne Rembrandt Dragon Range
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Lucienne 		Cezanne
Barceló 		Phoenix
Entry Dalí Mendocino
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge Pollock
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon 		Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family 		Prairie Falcon Banded Kestrel River Hawk
Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 2015 Jun 2015 Jun 2016 Oct 2017 Jan 2019 Mar 2020 Jan 2021 Jan 2022 Sep 2022 Jan 2023 Jan 2011 May 2013 Apr 2014 May 2015 Feb 2016 Apr 2019 Jul 2020 Jun 2022 Nov 2022
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[12] Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Bobcat Jaguar Puma Puma+[13] "Excavator+" Zen Zen+ "Zen 2+"
ISA x86-64 v1 x86-64 v2 x86-64 v3 x86-64 v4 x86-64 v1 x86-64 v2 x86-64 v3
Socket Desktop Performance — AM5 — —
Mainstream — AM4 — —
Entry FM1 FM2 FM2+ FM2+[a], AM4 AM4 —
Basic — — AM1 — FP5 —
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FP7 FL1 FP7
FP7r2
FP8 		? FT1 FT3 FT3b FP4 FP5 FT5 FP5 FT6
PCI Express version 2.0 3.0 4.0 5.0 4.0 2.0 3.0
CXL — —
Fab. (nm) GF 32SHP
(HKMG SOI) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N7
(FinFET bulk) 		TSMC N6
(FinFET bulk) 		CCD: TSMC N5
(FinFET bulk)
cIOD: TSMC N6
(FinFET bulk) 		TSMC 4nm
(FinFET bulk) 		TSMC N40
(bulk) 		TSMC N28
(HKMG bulk) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N6
(FinFET bulk)
Die area (mm2) 228 246 245 245 250 210[14] 156 180 210 CCD: (2x) 70
cIOD: 122 		178 75 (+ 28 FCH) 107 ? 125 149 ~100
Min TDP (W) 35 17 12 10 15 65 35 4.5 4 3.95 10 6 12 8
Max APU TDP (W) 100 95 65 45 170 54 18 25 6 54 15
Max stock APU base clock (GHz) 3 3.8 4.1 4.1 3.7 3.8 3.6 3.7 3.8 4.0 3.3 4.7 4.3 1.75 2.2 2 2.2 3.2 2.6 1.2 3.35 2.8
Max APUs per node[b] 1 1
Max core dies per CPU 1 2 1 1
Max CCX per core die 1 2 1 1
Max cores per CCX 4 8 2 4 2 4
Max CPU[c] cores per APU 4 8 16 8 2 4 2 4
Max threads per CPU core 1 2 1 2
Integer pipeline structure 3+3 2+2 4+2 4+2+1 1+3+3+1+2 1+1+1+1 2+2 4+2 4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF Yes Yes
IOMMU[d] — v2 v1 v2
BMI1, AES-NI, CLMUL, and F16C Yes — Yes
MOVBE — Yes
AVIC, BMI2, RDRAND, and MWAITX/MONITORX — Yes
SME[e], TSME[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing — Yes — Yes
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT — Yes — Yes
MPK, VAES — Yes —
SGX — —
FPUs per core 1 0.5 1 1 0.5 1
Pipes per FPU 2 2
FPU pipe width 128-bit 256-bit 80-bit 128-bit 256-bit
CPU instruction set SIMD level SSE4a[f] AVX AVX2 AVX-512 SSSE3 AVX AVX2
3DNow! 3DNow!+ — —
PREFETCH/PREFETCHW Yes Yes
GFNI — Yes —
AMX —
FMA4, LWP, TBM, and XOP — Yes — — Yes —
FMA3 Yes Yes
AMD XDNA — Yes —
L1 data cache per core (KiB) 64 16 32 32
L1 data cache associativity (ways) 2 4 8 8
L1 instruction caches per core 1 0.5 1 1 0.5 1
Max APU total L1 instruction cache (KiB) 256 128 192 256 512 256 64 128 96 128
L1 instruction cache associativity (ways) 2 3 4 8 2 3 4 8
L2 caches per core 1 0.5 1 1 0.5 1
Max APU total L2 cache (MiB) 4 2 4 16 1 2 1 2
L2 cache associativity (ways) 16 8 16 8
Max on--die L3 cache per CCX (MiB) — 4 16 32 — 4
Max 3D V-Cache per CCD (MiB) — 64 — —
Max total in-CCD L3 cache per APU (MiB) 4 8 16 64 4
Max. total 3D V-Cache per APU (MiB) — 64 — —
Max. board L3 cache per APU (MiB) — —
Max total L3 cache per APU (MiB) 4 8 16 128 4
APU L3 cache associativity (ways) 16 16
L3 cache scheme Victim Victim
Max. L4 cache — —
Max stock DRAM support DDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR5-4800, LPDDR5-6400 DDR5-5200 DDR5-5600, LPDDR5x-7500 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400 DDR4-1600 DDR4-3200 LPDDR5-5500
Max DRAM channels per APU 2 1 2 1 2
Max stock DRAM bandwidth (GB/s) per APU 29.866 34.132 38.400 46.932 68.256 102.400 83.200 120.000 10.666 12.800 14.933 19.200 38.400 12.800 51.200 88.000
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen[15] RDNA 2 RDNA 3 TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen[15] GCN 5th gen RDNA 2
GPU instruction set TeraScale instruction set GCN instruction set RDNA instruction set TeraScale instruction set GCN instruction set RDNA instruction set
Max stock GPU base clock (MHz) 600 800 844 866 1108 1250 1400 2100 2400 400 538 600 ? 847 900 1200 600 1300 1900
Max stock GPU base GFLOPS[g] 480 614.4 648.1 886.7 1134.5 1760 1971.2 2150.4 3686.4 102.4 86 ? ? ? 345.6 460.8 230.4 1331.2 486.4
3D engine[h] Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 Up to 704:44:16[16] Up to 512:32:8 768:48:8 128:8:4 80:8:4 128:8:4 Up to 192:12:8 Up to 192:12:4 192:12:4 Up to 512:?:? 128:?:?
IOMMUv1 IOMMUv2 IOMMUv1 ? IOMMUv2
Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0[17] VCN 2.1[18] VCN 2.2[18] VCN 3.1 ? UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.2 VCN 1.0 VCN 3.1
Video encoder — VCE 1.0 VCE 2.0 VCE 3.1 — VCE 2.0 VCE 3.4
AMD Fluid Motion No Yes No No Yes No
GPU power saving PowerPlay PowerTune PowerPlay PowerTune[19]
TrueAudio — Yes[20] ? — Yes
FreeSync 1
2 		1
2
HDCP[i] ? 1.4 2.2 2.3 ? 1.4 2.2 2.3
PlayReady[i] — 3.0 not yet — 3.0 not yet
Supported displays[j] 2–3 2–4 3 3 (desktop)
4 (mobile, embedded)		 4 2 3 4 4
/drm/radeon[k][22][23] Yes — Yes —
/drm/amdgpu[k][24] — Yes[25] — Yes[25]
  1. ^ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. ^ A PC would be one node.
  3. ^ An APU combines a CPU and a GPU. Both have cores.
  4. ^ Requires firmware support.
  5. ^ a b Requires firmware support.
  6. ^ No SSE4. No SSSE3.
  7. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. ^ Unified shaders : texture mapping units : render output units
  9. ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. ^ To feed more than two displays, the additional panels must have native DisplayPort support.[21] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

Operating system support

The VCE SIP core needs to be supported by the device driver. The device driver provides one or multiple interfaces, like e.g. OpenMAX IL. One of this interfaces is then used by end-user software, like e.g. GStreamer or HandBrake, to access the VCE hardware and make use of it.

AMD's proprietary device driver AMD Catalyst is available for multiple operating systems and support for VCE has been added to it[citation needed]. Additionally, a free device driver is available. This driver also supports the VCE hardware.

Linux

Support for the VCE ASIC is contained in the Linux kernel device driver amdgpu.
Main articles: AMD Catalyst for Linux and Free Radeon driver

Windows

The software "MediaShow Espresso Video Transcoding" seems to utilize VCE and UVD to the fullest extent possible.[30]

XSplit Broadcaster supports VCE from version 1.3.[31]

Open Broadcaster Software (OBS Studio) supports VCE for recording and streaming. The original Open Broadcaster Software (OBS) requires a fork build in order to enable VCE.[32]

Remotr (PC to Phone / Tablet Streaming Software) supports VCE for streaming, resulting in increased overall FPS during gameplay on the handheld device.[33]

See also

References

  1. ^ a b http://developer.amd.com/community/blog/2014/02/19/introducing-video-coding-engine-vce/
  2. ^ a b "Video & Movies: The Video Codec Engine, UVD3, & Steady Video 2.0". AnandTech.
  3. ^ http://www.amd.com/Documents/UVD3_whitepaper.pdf
  4. ^ "AnandTech Portal | AMD Radeon HD 7970 Review: 28nm And Graphics Core Next, Together As One". Anandtech.com. Retrieved 2014-03-27.
  5. ^ "AMD's Radeon HD 7970 graphics processor - The Tech Report - Page 5". The Tech Report. Retrieved 2014-03-27.
  6. ^ "Radeon HD 8900 Specs". AMD. Retrieved 2016-07-18.
  7. ^ http://lists.freedesktop.org/archives/dri-devel/2015-June/084083.html [pull] amdgpu drm-next-4.2
  8. ^ Rick Merritt (2015-01-05). "AMD Describes Notebook Processor". EE Times. Retrieved 2015-01-10.
  9. ^ http://wccftech.com/amd-embedded-roadmap-2014-2016-leaked-insight-gen-apus-gpus/ AMD Embedded Roadmap 2014-2016 Leaked – Gives Insight Into Next Gen 20nm APUs/SOCs and Discrete GPU Solutions
  10. ^ http://www.kitguru.net/components/graphic-cards/anton-shilov/key-features-of-amds-third-iteration-of-gcn-architecture-revealed/ Key features of AMD’s third iteration of GCN architecture revealed
  11. ^ http://www.xbitlabs.com/news/graphics/display/20140826114104_AMD_Quietly_Reveals_Third_Iteration_of_GCN_Architecture_with_Tonga_GPU.html AMD Quietly Reveals Third Iteration of GCN Architecture with Tonga GPU.
  12. ^ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  13. ^ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  14. ^ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  15. ^ a b "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  16. ^ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  17. ^ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  18. ^ a b "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021.
  19. ^ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  20. ^ "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  21. ^ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  22. ^ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
  23. ^ "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
  24. ^ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  25. ^ a b Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
  26. ^ König, Christian (4 February 2014). "initial VCE support". mesa-dev (Mailing list). Retrieved 28 November 2015.
  27. ^ König, Christian (24 October 2013). "OpenMAX state tracker". mesa-dev (Mailing list). Retrieved 28 November 2015.
  28. ^ "AMD Open-Sources VCE Video Encode Engine Code". Phoronix. 2014-02-04.
  29. ^ "st/omx/enc: implement h264 level support". 2014-06-12.
  30. ^ "MediaShow Espresso Video Transcoding Benchmark".
  31. ^ "XSplit Broadcaster 1.3 maintenance update includes mainly performance enhancements and maintenance fixes including such noteworthy features such as support for AMD's VCE H.264 hardware encoder".
  32. ^ "OBS branch with AMD VCE support".
  33. ^ "Remotr is able to utilise both AMD AMF/VCE and Nvidia NvENC technologies".
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