ARM Cortex-A5
| General information | |
|---|---|
| Designed by | ARM Holdings |
| Common manufacturer | |
| Cache | |
| L1 cache | 4-64 KB/4-64 KB |
| Architecture and classification | |
| Instruction set | ARMv7 |
| Physical specifications | |
| Cores |
|
The ARM Cortex-A5 is a processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture.
Overview
It is intended to replace the ARM9 and ARM11 cores for use in low-end devices.[1] Compared to those older cores, the Cortex-A5 offers the advanced features of the ARM v7 architecture over the v4/v5 (ARM9) and v6 (ARM11) architectures e.g. VFPv4 and NEON advanced SIMD. It also allows devices to run current software, which is increasingly focusing on ARM v7 and dropping support for earlier architectures.
Key features of the Cortex-A5 core are:
- Single-issue, in-order microarchitecture with an 8 stage pipeline[1]
- NEON SIMD instruction set extension (optional)
- VFPv4 floating-point unit (optional)
- Thumb-2 instruction set encoding
- Jazelle RCT
- 1.57 DMIPS / MHz
Chips
Several system-on-chips (SoC) have implemented the Cortex-A5 core, including:
- Atmel SAMA5D3
- Freescale Vybrid Series
- Snapdragon S4 Play
- Spreadtrum SC8810 (single core A5 1GHz + Mali400 GPU)
- Actions Semiconductor ATM7029 (gs702a) is a quad-core Cortex-A5 configuration
- 2013 AMD Fusion APUs will include a Cortex-A5 as a security co-processor[2]
See also
- Comparison of ARMv7-A cores
- ARM architecture
- List of ARM microprocessor cores
- List of applications of ARM cores
- JTAG
References
- ^ a b Jon Stokes (Oct 23, 2009). "ARM fills out CPU lineup with Cortex A5". Ars Technica. Retrieved 2012-10-18.
- ^ Ryan Smith (2012-06-13). "AMD 2013 APUs To Include ARM Cortex-A5 Processor For TrustZone Capabilities". AnandTech. Retrieved 2012-10-17.
External links
- ARM Holdings