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ARM Cortex-M

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ARM Cortex-M0 and Cortex-M3 microcontroller ICs from NXP and Silicon Labs (Energy Micro)
Die from a STM32F100C4T6B IC.
24 MHz ARM Cortex-M3 microcontroller with 16 KB flash memory, 4 KB RAM. Manufactured by STMicroelectronics.

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. The cores are intended for microcontroller use. The cores consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33.[1][2][3][4][5][6][7] The Cortex-M4 / M7 / M33 cores have an FPU option, and these cores are known as "Cortex-Mx with FPU" or Cortex-MxF, where 'x' is the core number. ARM Cortex-M cores have been shipped in tens of billions of devices.[8]

Overview

Announced
Year Core
2004 Cortex-M3
2007 Cortex-M1
2009 Cortex-M0
2010 Cortex-M4(F)
2012 Cortex-M0+
2014 Cortex-M7(F)
2016 Cortex-M23
2016 Cortex-M33(F)
See also: ARM architecture and List of ARM cores

The ARM Cortex-M family are ARM microprocessor cores which are designed for use in microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and sensors controllers.

Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward. Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, and replacing older legacy ARM cores such as ARM7 and ARM9.

License

Arm Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Some of the most important options for the Cortex-M cores are:

  • SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.[9][10][11] Though the SysTick timer is optional, it is very rare to find a Cortex-M microcontroller without it. If a Cortex-M33 microcontroller has the Security Extension option, then it has two SysTicks, one Secure and one Non-secure.
  • Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address, and individual bits to be toggled from C/C++ without performing a read-modify-write sequence of instructions.[9][10][11] Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.
  • Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions.[9][10][11]
  • Tightly-Coupled Memory (TCM): Low-latency RAM that is used to hold critical routines, data, stacks. It is typically the fastest memory in the microcontroller.
ARM Cortex-M optional components
ARM Core Cortex
M0[1]		 Cortex
M0+[2]		 Cortex
M1[3]		 Cortex
M3[4]		 Cortex
M4[5]		 Cortex
M7[6]		 Cortex
M23[7]		 Cortex
M33[12]
SysTick 24-bit Timer Optional
(0,1)		 Optional
(0,1)		 Optional
(0,1)		 Yes
(1)		 Yes
(1)		 Yes
(1)		 Optional
(0,1,2)		 Yes
(1,2)
Single-cycle I/O port No Optional No No No No Optional No
Bit-Band memory No[13] No[13] No* Optional Optional No No No
Memory Protection
Unit (MPU)		 No Optional
(0,8)		 No Optional
(0,8)		 Optional
(0,8)		 Optional
(0,8,16)		 Optional
(0,4,8,12,16)		 Optional
(0,4,8,12,16)
Security Attribution
Unit (SAU)		 No No No No No No Optional
(0,4,8)		 Optional
(0,4,8)
Instruction TCM No No Optional No No Optional No TBD
Data TCM No No Optional No No Optional No TBD
Instruction Cache No[14] No[14] No[14] No[14] No[14] Optional No TBD
Data Cache No[14] No[14] No[14] No[14] No[14] Optional No TBD
Vector Table Offset
Register (VTOR)		 No Optional
(0,1)		 Optional
(0,1)		 Optional
(0,1)		 Optional
(0,1)		 Optional
(0,1)		 Optional
(0,1,2)		 Yes
(1,2)
  • Note: Most Cortex-M3 and M4 chips have bit-band and MPU. The bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit.[13]
  • Note: Software should validate the existence of a feature before attempting to use it.[11]

Additional silicon options:[9][10]

  • Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.
  • Interrupts: 1 to 32 (M0/M0+/M1), 1 to 240 (M3/M4/M7/M23), 1 to 480 (M33).
  • Wake-up interrupt controller: Optional.
  • Vector Table Offset Register: Optional. (not available for M0).
  • Instruction fetch width: 16-bit only, or mostly 32-bit.
  • User/privilege support: Optional.
  • Reset all registers: Optional.
  • Single-cycle I/O port: Optional. (M0+/M23).
  • Debug Access Port (DAP): None, SWD, JTAG and SWD. (optional for all Cortex-M cores)
  • Halting debug support: Optional.
  • Number of watchpoint comparators: 0 to 2 (M0/M0+/M1), 0 to 4 (M3/M4/M7/M23/M33).
  • Number of breakpoint comparators: 0 to 4 (M0/M0+/M1/M23), 0 to 8 (M3/M4/M7/M33).

Instruction sets

See also: ARM architecture § Instruction set

The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture,[9] the Cortex-M3 implements the ARMv7-M architecture,[10] and the Cortex-M4 / Cortex-M7 implements the ARMv7E-M architecture.[10] The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33.[9][10] Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures, but the legacy 32-bit ARM instruction set isn't supported.

All six Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.

The Cortex-M0 / Cortex-M0+ / Cortex-M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / Cortex-M0+ / Cortex-M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR). The Cortex-M3 / M4 / M7 / M33 have all base Thumb-1 and Thumb-2 instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).[9][10]

ARM Cortex-M instruction variations
Arm Core Cortex
M0[1]		 Cortex
M0+[2]		 Cortex
M1[3]		 Cortex
M3[4]		 Cortex
M4[5]		 Cortex
M7[6]		 Cortex
M23[7]		 Cortex
M33[12]
ARM architecture ARMv6-M[9] ARMv6-M[9] ARMv6-M[9] ARMv7-M[10] ARMv7E-M[10] ARMv7E-M[10] ARMv8-M[15] ARMv8-M[15]
Computer architecture Von Neuman Von Neumann Von Neumann Harvard Harvard Harvard Von Neumann Harvard
Instruction pipeline 3 stages 2 stages 3 stages 3 stages 3 stages 6 stages 2 stages 3 stages
Thumb-1 instructions Most Most Most Entire Entire Entire Most Entire
Thumb-2 instructions Some Some Some Entire Entire Entire Some Entire
Multiply instructions 32-bit result 32-bit result 32-bit result 32-bit result
64-bit result		 32-bit result
64-bit result		 32-bit result
64-bit result		 32-bit result 32-bit result
64-bit result
Divide instructions No No No Yes Yes Yes Yes Yes
Saturated instructions No No No Some Yes Yes No Yes
DSP instructions No No No No Yes Yes No Optional
Floating-point instructions No No No No Optional: SP Optional: SP
or SP & DP		 No Optional: SP
TrustZone instructions No No No No No No Optional Optional
  • Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit Thumb-1 instructions: CBZ, CBNZ, IT.[9][10]
  • Note: The Cortex-M0 / M0+ / M1 only include these 32-bit Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.[9][10]
  • Note: The Cortex-M0 / M0+ / M1 / M23 only has 32-bit multiply instructions with a lower-32-bit result (32bit × 32bit = lower 32bit), where as the Cortex-M3 / M4 / M7 / M33 includes additional 32-bit multiply instructions with 64-bit results (32bit × 32bit = 64bit). The Cortex-M4 / M7 / M33 also include DSP instructions for (16bit × 16bit = 32bit), (32bit × 16bit = upper 32bit), (32bit × 32bit = upper 32bit) multiplications. If a smaller silicon die is required, the Cortex-M0 / M0+ / M1 has an option to be a much slower instruction, though it is rarely implemented in the M0 or M0+.[9][10]
  • Note: The Cortex-M4 and M33 has a silicon FPU option of single-precision (SP). The Cortex-M7 has silicon FPU options of single-precision (SP), or both single-precision (SP) and double-precision (DP). If the Cortex-M4 / M7 / M33 has a FPU, then it is known as the Cortex-M4F / Cortex-M7F / Cortex-M33F.[9][10]
  • Note: The Cortex-M series includes three new 16-bit Thumb-1 instructions for sleep mode: SEV, WFE, WFI.
ARM Cortex-M instruction groups
Group Instr
bits		 Instructions Cortex
M0		 Cortex
M0+		 Cortex
M1		 Cortex
M3		 Cortex
M4		 Cortex
M7		 Cortex
M23		 Cortex
M33
Thumb-1 16 ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STMIA, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD Yes Yes Yes Yes Yes Yes Yes Yes
Thumb-1 16 CBNZ, CBZ No No No Yes Yes Yes Yes Yes
Thumb-1 16 IT No No No Yes Yes Yes No Yes
Thumb-2 32 BL, DMB, DSB, ISB, MRS, MSR Yes Yes Yes Yes Yes Yes Yes Yes
Thumb-2 32 ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, CLZ, CMN, CMP, DBG, EOR, LDC, LDMA, LDMDB, LDR, LDRB, LDRBT, LDRD, LDREX, LDREXB, LDREXH, LDRH, LDRHT, LDRSB, LDRSBT, LDRSHT, LDRSH, LDRT, MCR, LSL, LSR, MLS, MCRR, MLA, MOV, MOVT, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SEV, SMLAL, SMULL, SSAT, STC, STMDB, STR, STRB, STRBT, STRD, STREX, STREXB, STREXH, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD No No No Some Yes Yes No Yes
Thumb-2 32 SDIV, UDIV No No No Yes Yes Yes Yes Yes
DSP 32 PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16 No No No No Yes Yes No Optional
SP Float 32 VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUB No No No No Optional
SP FPU		 Optional
SP FPU		 No Optional
SP FPU
DP Float 32 VCVTA, VCVTM, VCVTN, VCVTP, VMAXNM, VMINNM, VRINTA, VRINTM, VRINTN, VRINTP, VRINTR, VRINTX, VRINTZ, VSEL No No No No No Optional
DP FPU		 No No
TrustZone 16 BLXNS, BXNS No No No No No No Optional Optional
TrustZone 32 SG, TT, TTT, TTA, TTAT No No No No No No Optional Optional
  • Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4/M7/M33 only when the SP FPU option exists in the silicon.
  • Note: The double-precision (DP) FPU instructions are valid in the Cortex-M7 only when the DP FPU option exists in the silicon.

Deprecations

The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:[9][10]

  • The 32-bit ARM instruction set is not included in Cortex-M cores.
  • Endianness is chosen at silicon implementation in Cortex-M cores. Legacy cores allowed "on-the-fly" changing of the data endian mode.
  • Co-processors aren't supported on Cortex-M cores.

The capabilities of the 32-bit ARM instruction set is duplicated in many ways by the Thumb-1 and Thumb-2 instruction sets, but some ARM features don't have a similar feature:

  • The SWP and SWPB (swap) ARM instructions don't have a similar feature in Cortex-M.

The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy ARM7T cores with the ARMv4T architecture. New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores:

  • "BLX <immediate>" instruction doesn't exist because it was used to switch from Thumb-1 to ARM instruction set. The "BLX <register>" instruction is still available in the Cortex-M.
  • SETEND doesn't exist because on-the-fly switching of data endian mode is no longer supported.
  • Co-processor instructions are not supported.
  • SWI instruction was renamed to SVC instruction, though the instruction binary coding is the same. However, the SVC handler code is different than SWI handler because of changes to the exception models.

Cortex-M0

Cortex-M0
Architecture and classification
MicroarchitectureARMv6-M
Instruction setThumb-1 (most),
Thumb-2 (some)

The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.

Key features of the Cortex-M0 core are:[1]

  • ARMv6-M architecture[9]
  • 3-stage pipeline.
  • Instruction sets:
    • Thumb-1 (most), missing CBZ, CBNZ, IT.
    • Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
    • 32-bit hardware integer multiply with 32-bit result.
  • 1 to 32 interrupts, plus NMI.

Silicon options:

  • Hardware integer multiply speed: 1 or 32 cycles.

Chips

The following microcontrollers are based on the Cortex-M0 core:

The following chips have a Cortex-M0 as a secondary core:

  • NXP LPC4300 (one Cortex-M4F + one Cortex-M0)
  • Texas Instruments SimpleLink Wireless MCUs CC1310 and CC2650 (one programmable Cortex-M3 + one Cortex-M0 network processor + one proprietary Sensor Controller Engine)

Cortex-M0+

Cortex-M0+
Architecture and classification
MicroarchitectureARMv6-M
Instruction setThumb-1 (most),
Thumb-2 (some)
NXP (Freescale) FRDM-KL25Z Board with KL25Z128VLK (Kinetis L)

The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools. The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the memory protection unit (MPU) and the vector table relocation.[2]

Key features of the Cortex-M0+ core are:[2]

  • ARMv6-M architecture[9]
  • 2-stage pipeline (one fewer than Cortex-M0).
  • Instruction sets: (same as Cortex-M0)
    • Thumb-1 (most), missing CBZ, CBNZ, IT.
    • Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
    • 32-bit hardware integer multiply with 32-bit result.
  • 1 to 32 interrupts, plus NMI.

Silicon options:

  • Hardware integer multiply speed: 1 or 32 cycles.
  • 8 region memory protection unit (MPU) (same as M3 and M4).
  • Vector table relocation (same as M3, M4).
  • Single-cycle I/O port (available in M0+/M23).
  • Micro Trace Buffer (MTB) (available in M0+/M23/M33).

Chips

The following microcontrollers are based on the Cortex-M0+ core:

The smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6 mm by 2 mm is Kinetis KL03)[16]

Cortex-M1

Cortex-M1
Architecture and classification
MicroarchitectureARMv6-M
Instruction setThumb-1 (most),
Thumb-2 (some)

The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips.

Key features of the Cortex-M1 core are:[3]

  • ARMv6-M architecture[9]
  • 3-stage pipeline.
  • Instruction sets:
    • Thumb-1 (most), missing CBZ, CBNZ, IT.
    • Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
    • 32-bit hardware integer multiply with 32-bit result.
  • 1 to 32 interrupts, plus NMI.

Silicon options:

  • Hardware integer multiply speed: 3 or 33 cycles.
  • Optional Tightly-Coupled Memory (TCM): 0 to 1 MB instruction-TCM, 0 to 1 MB data-TCM, each with optional ECC.
  • External interrupts: 0, 1, 8, 16, 32.
  • Debug: none, reduced, full.
  • Data endianness: little-endian or BE-8 big-endian.
  • OS extension: present or absent.

Chips

The following vendors support the Cortex-M1 as soft-cores on their FPGA chips:

  • Altera Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
  • Microsemi (Actel) Fusion, IGLOO/e, ProASIC3L, ProASIC3/E
  • Xilinx Spartan-3, Virtex-2, Virtex-3, Virtex-4

Cortex-M3

Cortex-M3
Architecture and classification
MicroarchitectureARMv7-M
Instruction setThumb-1, Thumb-2,
Saturated (some)
Arduino Due board with Atmel ATSAM3X8E (ARM Cortex-M3 core) microcontroller
NXP LPCXpresso Development Board with LPC1343

Key features of the Cortex-M3 core are:[4][17]

  • ARMv7-M architecture[10]
  • 3-stage pipeline with branch speculation.
  • Instruction sets:
    • Thumb-1 (entire).
    • Thumb-2 (entire).
    • 32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit multiply is 1 cycle, but 64-bit multiply and MAC instructions require extra cycles.
    • 32-bit hardware integer divide (2-12 cycles).
    • saturation arithmetic support.
  • 1 to 240 interrupts, plus NMI.
  • 12 cycle interrupt latency.
  • Integrated sleep modes.

Silicon options:

  • Optional Memory Protection Unit (MPU): 0 or 8 regions.

Chips

The following microcontrollers are based on the Cortex-M3 core:

The following chips have a Cortex-M3 as a secondary core:

The following FPGAs include a Cortex-M3 core:

Cortex-M4

Cortex-M4(F)
Architecture and classification
MicroarchitectureARMv7E-M
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
FPU (SP)
Silicon Labs (Energy Micro) Wonder Gecko STK Board with EFM32WG990
TI Stellaris Launchpad Board with LM4F120

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP instructions, and optional floating-point unit (FPU). If a core contains an FPU, it is known as a Cortex-M4F, otherwise it is a Cortex-M4.

Key features of the Cortex-M4 core are:[5]

  • ARMv7E-M architecture[10]
  • 3-stage pipeline with branch speculation.
  • Instruction sets:
    • Thumb-1 (entire).
    • Thumb-2 (entire).
    • 32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit Multiply and MAC are 1 cycle.
    • 32-bit hardware integer divide (2-12 cycles).
    • Saturation arithmetic support.
    • DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
  • 1 to 240 interrupts, plus NMI.
  • 12 cycle interrupt latency.
  • Integrated sleep modes.

Silicon options:

  • Optional floating-point unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv4-SP extension.
  • Optional memory protection unit (MPU): 0 or 8 regions.

Chips

The following microcontrollers are based on the Cortex-M4 core:

The following microcontrollers are based on the Cortex-M4F (M4 + FPU) core:

The following chips have either a Cortex-M4 or M4F as a secondary core:

Cortex-M7

Cortex-M7(F)
Architecture and classification
MicroarchitectureARMv7E-M
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
FPU (SP & DP)

The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline with branch prediction and an optional floating-point unit capable of single-precision and optionally double-precision operations.[21][22] The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a Cortex-M7.

Key features of the Cortex-M7 core are:[6]

  • ARMv7E-M architecture.
  • 6-stage pipeline with branch speculation.
  • Instruction sets:
    • Thumb-1 (entire).
    • Thumb-2 (entire).
    • 32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit Multiply and MAC are 1 cycle.
    • 32-bit hardware integer divide (2-12 cycles).
    • Saturation arithmetic support.
    • DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
  • 1 to 240 interrupts, plus NMI.
  • 12 cycle interrupt latency.
  • Integrated sleep modes.

Silicon options:

  • Optional Floating-Point Unit (FPU): (single precision) or (single and double-precision), both IEEE-754-2008 compliant. It is called the FPv5 extension.
  • Optional CPU cache: 0 to 64 KB instruction-cache, 0 to 64 KB data-cache, each with optional ECC.
  • Optional Tightly-Coupled Memory (TCM): 0 to 16 MB instruction-TCM, 0 to 16 MB data-TCM, each with optional ECC.
  • Optional Memory Protection Unit (MPU): 8 or 16 regions.
  • Optional Embedded Trace Macrocell (ETM): instruction-only, or instruction and data.
  • Optional Retention Mode (with Arm Power Management Kit) for Sleep Modes.

Chips

The following microcontrollers are based on the Cortex-M7 core:

Cortex-M23

Cortex-M23
Architecture and classification
MicroarchitectureARMv8-M
Instruction setThumb-1 (most),
Thumb-2 (some),
Divide, TrustZone

The Cortex-M23 core was announced in October 2016[25] and based on the newer ARMv8-M architecture that was previously announced in November 2015.[26] Conceptually the Cortex-M23 is similar to a Cortex-M0+ plus integer divide instructions and TrustZone security features, and also has a 2-stage instruction pipeline.

As of April 2018, the "Arm Cortex-M23 Arm Generic User Guide" is not yet available from Arm Holdings, though the "Arm Cortex-M23 Technical Reference Manual" is available.

Key features of the Cortex-M23 core are:[7][25]

  • ARMv8-M architecture.[15]
  • 2-stage pipeline (similar to Cortex-M0+).
  • TrustZone security instructions. (available only in M23/M33)
  • 32-bit hardware integer divide (17 or 34 cycles). (not available in M0/M0+/M1) (slower than M3/M4/M7/M33)
  • TBD.

Silicon options:

  • Hardware integer multiply speed: 1 or 32 cycles.
  • Hardware integer divide speed: 17 or 34 cycles maximum. Depending on divisor, instruction may complete in fewer cycles.
  • Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
  • Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
  • Single-cycle I/O port (available in M0+/M23).
  • Micro Trace Buffer (MTB) (available in M0+/M23/M33).
  • TBD.

Chips

The following microcontrollers are based on the Cortex-M23 core:

  • No chips available yet.
  • Nuvoton M2351 (announced, not yet generally available).[2]
  • Expected future chips from Microchip, Nuvoton, NXP, Renesas, Silicon Labs, STMicroelectronics.[25]

Cortex-M33

Cortex-M33(F)
Architecture and classification
MicroarchitectureARMv8-M
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
Divide, FPU (SP),
TrustZone

The Cortex-M33 core was announced in October 2016[25] and based on the newer ARMv8-M architecture that was previously announced in November 2015.[26] Conceptually the Cortex-M33 is similar to a cross of Cortex-M4 and Cortex-M23, and also has a 3-stage instruction pipeline.

Key features of the Cortex-M33 core are:[12][25]

  • ARMv8-M architecture.[15]
  • 3-stage pipeline.
  • TrustZone security instructions. (available only in M23/M33)
  • 32-bit hardware integer divide (11 cycles maximum). (not available in M0/M0+/M1)
  • Stack limit register.
  • TBD.

Silicon options:

  • Optional Floating-Point Unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv5 extension.
  • Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
  • Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
  • Micro Trace Buffer (MTB) (available in M0+/M23/M33).
  • TBD.

Chips

The following microcontrollers are based on the Cortex-M33 core:

  • Nordic nRF91 (announced, not yet generally available)[27]
  • Expected future chips from Analog Devices, NXP, Renesas, Silicon Labs, STMicroelectronics.[25]

Development tools

Segger J-Link PRO. Debug probe with SWD or JTAG interface to target ARM chip, and USB or Ethernet interfaces to host computer.
Main article: List of ARM Cortex-M development tools

Documentation

The amount of documentation for all Arm chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all Arm chips since it consists of documents from the IC manufacturer and documents from CPU core vendor (Arm Holdings).

A typical top-down documentation tree is:

Documentation tree (top to bottom)
  1. IC manufacturer website
  2. IC manufacturer marketing slides
  3. IC manufacturer datasheet for the exact physical chip
  4. IC manufacturer reference manual that describes common peripherals and aspects of a physical chip family
  5. ARM core website
  6. ARM core generic user guide
  7. ARM core technical reference manual that describes the instruction set(s)
  8. ARM architecture reference manual

IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External Links section for links to official Arm documents.

See also

References

  1. ^ a b c d Cortex-M0 r0p0 Technical Reference Manual; Arm Holdings.
  2. ^ a b c d e Cortex-M0+ r0p0 Technical Reference Manual; Arm Holdings.
  3. ^ a b c d Cortex-M1 r1p0 Technical Reference Manual; Arm Holdings.
  4. ^ a b c d Cortex-M3 r2p1 Technical Reference Manual; Arm Holdings.
  5. ^ a b c d Cortex-M4 r0p1 Technical Reference Manual; Arm Holdings.
  6. ^ a b c d Cortex-M7 r0p2 Technical Reference Manual; Arm Holdings.
  7. ^ a b c d Cortex-M23 r1p0 Technical Reference Manual; Arm Holdings.
  8. ^ ARM Cortex-M website; arm.com
  9. ^ a b c d e f g h i j k l m n o p q r ARMv6-M Architecture Reference Manual; Arm Holdings.
  10. ^ a b c d e f g h i j k l m n o p q r ARMv7-M Architecture Reference Manual; Arm Holdings.
  11. ^ a b c d Cortex-M3 Embedded Software Development; App Note 179; Arm Holdings.
  12. ^ a b c Cortex-M33 r0p3 Technical Reference Manual; Arm Holdings.
  13. ^ a b c Cortex-M System Design Kit; Arm Holdings.
  14. ^ a b c d e f g h i j ARM Cortex-M Programming Guide to Memory Barrier Instructions; Section 3.6 System implementation requirements; AppNote 321; arm.com
  15. ^ a b c d ARMv8-M Architecture Reference Manual; Arm Holdings.
  16. ^ Fingas, Jon (25 February 2014). "Freescale makes the world's smallest ARM controller chip even tinier". Retrieved 2 October 2014.
  17. ^ Sadasivan, Shyam. "An Introduction to the ARM Cortex-M3 Processor" (PDF). Arm Holdings. Archived from the original (PDF) on July 26, 2014. {{cite web}}: Unknown parameter |deadurl= ignored (|url-status= suggested) (help)
  18. ^ http://datasheets.gpio.dk/dl/RTL8710%20wifi%20module%20specification.pdf#page=11
  19. ^ "The Samsung Exynos 7420 Deep Dive - Inside A Modern 14nm SoC". AnandTech. Retrieved 2015-06-15.
  20. ^ "Microchip Launches Two New SAM Microcontroller Families with Extensive Connectivity Interface Options". www.microchip.com. Retrieved 2018-02-01.
  21. ^ "Cortex-M7 Processor". Arm Holdings. Retrieved 2014-09-24.
  22. ^ Press Release - ARM Supercharges MCU Market with High Performance Cortex-M7 Processor; arm.com; September 24, 2014;
  23. ^ "KV5x: Kinetis KV5x - 240 MHz, ARM® Cortex®-M7, Real-Time Control, Ethernet, Motor Control and Power Conversion, High-Performance Microcontrollers (MCUs)". Freescale Semiconductor. Retrieved 2015-04-09.
  24. ^ "STM32 F7 series of very high performance MCUs with ARM® Cortex®-M7 core". STMicroelectronics. Retrieved 2014-09-24.
  25. ^ a b c d e f New ARM Cortex-M processors offer the next industry standard for secure IoT; Arm Holdings; October 25, 2016.
  26. ^ a b ARMv8-M Architecture Simplifies Security for Smart Embedded Devices; Arm Holdings; November 10, 2015.
  27. ^ https://www.nordicsemi.com/News/News-releases/Product-Related-News/Nordic-nRF91-low-power-cellular-IoT-sneak-peek-cellular-made-easy-cellular-for-everything-else

Further reading

  • Designer's Guide to the Cortex-M Processor Family; 2nd Edition; Trevor Martin; 490 pages; 2016; ISBN 978-0081006290.
  • ARM Assembly for Embedded Applications; 3rd Edition; Daniel Lewis; 318 pages; 2017; ISBN 978-1543908046.
  • Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C; 2nd Edition; Yifeng Zhu, 660 pages; 2015; ISBN 978-0982692639.
  • Definitive Guide to the ARM Cortex-M0 and Cortex-M0+ Processors; 2nd Edition; Joseph Yiu; 784 pages; 2015; ISBN 978-0128032770.
  • Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors; 3rd Edition; Joseph Yiu; 600 pages; 2013; ISBN 978-0124080829.
  • Embedded Systems with ARM Cortex-M3 Microcontrollers in Assembly Language and C; 1st Edition; Yifeng Zhu; 542 pages; 2014; ISBN 978-0982692622.
  • Digital Signal Processing and Applications Using the ARM Cortex-M4; 1st Edition; Donald Reay; 250 pages; 2014; ISBN 978-1118859049.
  • Embedded Systems: Introduction to ARM Cortex-M Microcontrollers; 5th Edition; Jonathan Valvano; 506 pages; 2012; ISBN 978-1477508992.
  • Assembly Language Programming: ARM Cortex-M3; 1st Edition; Vincent Mahout; 256 pages; 2012; ISBN 978-1848213296.
  • Introduction To Reverse Engineering for Beginners including ARM assembly; Dennis Yurichev; online book.
Wikimedia Commons has media related to ARM Cortex-M.
ARM Cortex-M official documents
ARM
Core		 Bit
Width		 ARM
Website		 ARM Generic
User Guide		 ARM Technical
Reference Manual		 ARM Architecture
Reference Manual
Cortex-M0 32 Link Link Link ARMv6-M
Cortex-M0+ 32 Link Link Link ARMv6-M
Cortex-M1 32 Link Link Link ARMv6-M
Cortex-M3 32 Link Link Link ARMv7-M
Cortex-M4(F) 32 Link Link Link ARMv7E-M
Cortex-M7(F) 32 Link Link Link ARMv7E-M
Cortex-M23 32 Link — Link ARMv8-M
Cortex-M33(F) 32 Link Link Link ARMv8-M
Quick Reference Cards
  • Instructions: Thumb-1 (1), ARM and Thumb-2 (2), Vector Floating-Point (3) - arm.com
  • Opcodes: Thumb-1 (1, 2), ARM (3, 4), GNU Assembler Directives (5).
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