Template:Infobox CPU/testcases

Testing sandbox version {{Infobox CPU/sandbox}} MOS Technology 6502 A MOS 6502 processor in a DIP-40 plastic package. The four-digit date code indicates it was made in the 45th week of 1985 General information Launched 1975 (1975) Common manufacturer(s) MOS Technology, Rockwell, Synertek Performance Max. CPU clock rate 1 MHz to 2 MHz Data width 8 Address width 16 Architecture and classification Instruction set MOS 6502 Instructions 56 Physical specifications Package(s) 40-pin DIP Infobox CPU/testcases An Intel A80286-8 processor with a gray ceramic heat spreader General information Launched February 1982 Discontinued 1991 Common manufacturer(s) Intel, IBM, AMD, Harris (Intersil), Siemens, Fujitsu Performance Max. CPU clock rate 4 MHz to 25 MHz FSB speeds 4 MHz to 25 MHz Data width 16 bits Address width 24 bits Architecture and classification Technology node 1.5 µm Instruction set x86-16 (with MMU) Physical specifications Transistors 120,000 or 134,000, 1.5µm Co-processor Intel 80287 Package(s) 68-pin PLCC 68-pin LCC 68-pin PGA 100-pin PQFP (engineering sample only) Socket(s) PGA68 PLCC-68 LCC-68 History Predecessor 8086, 8088 (while 80186 was contemporary) Successor Intel 80386 Support status Unsupported Pentium (i586) General information Launched March 22, 1993 Discontinued July 15, 1999 Performance Max. CPU clock rate 60–300 MHz FSB speeds 50–66 MHz Cache L1 cache 16–32 KiB Architecture and classification Microarchitecture P5 Instruction set IA-32 Extensions MMX Physical specifications Transistors 3.1M 0.8 μm (P5) 3.2M 0.6 μm (P54C) 3.3M 350 nm (P54CS) 4.5M 350 nm (P55C) Cores 1 Socket(s) Socket 4 Socket 5 Socket 7 Products, models, variants Model(s) Pentium series Pentium OverDrive series Pentium MMX series History Predecessor i486 Successor P6, Pentium II Support status Unsupported P6 Die shot of Deschutes core General information Launched November 1, 1995 (November 1, 1995) Performance Max. CPU clock rate 150 MHz to 1.40 GHz FSB speeds 66 MHz to 133 MHz Cache L1 cache Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache) Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache) L2 cache 128 KB to 512 KB 256 KB to 2048 KB (Xeon) Architecture and classification Microarchitecture P6 Instruction set x86 Extensions MMX (Pentium II/III) SSE (Pentium III) Physical specifications Transistors 5.5M 500 nm 7.5M 350 nm 7.5M 250 nm (B0, B1) 9.5M 250 nm (B0, C0) 19M 250 nm (B0) 28M 180 nm (A1, A2, B0, C0, D0) 44M 130 nm (A1, B1, C1, D0) Cores 1 Socket(s) Socket 8 Slot 1 Socket 370 Socket 479 Products, models, variants Model(s) Celeron Series Pentium II Series Pentium III Series Pentium Pro Series Pentium II Xeon Series Pentium III Xeon Series Variant(s) Pentium M Enhanced Pentium M History Predecessor P5 Successor NetBurst, Pentium M Support status Unsupported P6 Pentium M General information Launched March 12, 2003 Performance Max. CPU clock rate 600 MHz to 2.26 GHz FSB speeds 400 MT/s to 533 MT/s Cache L1 cache 64KB (32 KB I Cache + 32 KB D cache) L2 cache 512 KB to 2048 KB Architecture and classification Microarchitecture P6 Instruction set x86 Extensions MMX, SSE, SSE2 Physical specifications Transistors 77M 130 nm (B1, B2) 144M 90 nm (B0, C0) 151M 65 nm (C0, D0) Cores 1 Socket(s) Socket M Products, models, variants Model(s) A100 Series EP80579 Series Celeron M Series Pentium M Series History Predecessor NetBurst Successor Enhanced Pentium M Support status Unsupported P6 Enhanced Pentium M General information Launched 2006 Performance Max. CPU clock rate 1.06 GHz to 2.33 GHz FSB speeds 533 MT/s to 667 MT/s Cache L1 cache 64 KB L2 cache 1 MB to 2 MB 2 MB (Xeon) Architecture and classification Microarchitecture P6 Instruction set x86 Extensions MMX, SSE, SSE2, SSE3 Physical specifications Transistors 151M 65 nm (C0, D0) Cores 1-2 Socket(s) Socket M Products, models, variants Model(s) Celeron M Series Pentium Dual-Core Series Core Solo Series Core Duo Series Xeon LV Series History Predecessor Pentium M Successor Intel Core Support status Unsupported NetBurst General information Launched November 20, 2000 (November 20, 2000) Performance Max. CPU clock rate 1.3 GHz to 3.8 GHz FSB speeds 400 MT/s to 1066 MT/s Cache L1 cache 8 KB to 16 KB per core L2 cache 128 KB to 2048 KB L3 cache 4 MB to 16 MB shared Architecture and classification Microarchitecture NetBurst Instruction set x86 (IA-32), x86-64 (some) Extensions MMX, SSE, SSE2, SSE3 (some) Physical specifications Transistors 42M 180 nm (B2, C1, D0, E0) 55M 130 nm (B0, C1, D1, M0) 125M 90 nm (C0, D0, E0, G1) 169M 90 nm (M0, N0, R0) 230M 90 nm (A0, B0) 188M 65 nm (B1, C1, D0) 376M 65 nm (B1, C1, D0) 1,328M 65 nm (B0) Cores 1-2 (2-4 threads with HT) Socket(s) Socket 423 Socket 478 Socket 603 Socket 604 LGA 771 LGA 775 Products, models, variants Model(s) Celeron Series Celeron D Series Pentium 4 Series Pentium D Series Xeon Series History Predecessor P6 Successor Intel Core IA-64 Intel Core General information Launched June 26, 2006 (June 26, 2006) (Xeon) July 27, 2006 (July 27, 2006) (Core 2) Performance Max. CPU clock rate 933 MHz to 3.5 GHz FSB speeds 533 MT/s to 1600 MT/s Cache L1 cache 64 KB per core L2 cache 0.5 to 6 MB per two cores L3 cache 8 MB to 16 MB shared (Xeon 7400) Architecture and classification Technology node 65 nm to 45 nm Microarchitecture Core Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4 (45nm Core 2 only), VT-x (some) Physical specifications Transistors 105M to 582M (65 nm) 228M to 1900M (45 nm) Cores 1–4 (2-6 Xeon) Socket(s) Socket M (µPGA 478) Socket P (µPGA 478) Socket T (LGA 775) Socket J (LGA 771) Socket 604 FCBGA (µBGA 479) FCBGA (µBGA 965) Products, models, variants Model(s) P6 family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon) History Predecessor NetBurst Enhanced Pentium M (P6) Successor Penryn (tick) (a version of Core) Nehalem (tock) Support status Unsupported Penryn General information Launched November 2007 (November 2007) Performance Max. CPU clock rate 1.06 GHz to 3.33 GHz FSB speeds 533 MT/s to 1600 MT/s Cache L1 cache 64 KB per core L2 cache 1 MB to 12 MB unified L3 cache 8 MB to 16 MB shared (Xeon) Architecture and classification Microarchitecture Core Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1 VT-x, VT-d Physical specifications Transistors 228M to 820M 45 nm Cores 1-4 (2-6 Xeon) Socket(s) Socket M (µPGA 478) Socket P (µPGA 478) Socket T (LGA 775) FCBGA (μBGA 479) FCBGA (μBGA 965) Products, models, variants Model(s) P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon) History Predecessor Core Successor Nehalem Support status Unsupported Nehalem General information Launched November 11, 2008 (November 11, 2008) Performance Max. CPU clock rate 1.06 GHz to 3.33 GHz QPI speeds 4.80 GT/s to 6.40 GT/s DMI speeds 2.50 GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 MB to 24 MB shared Architecture and classification Technology node 45 nm Microarchitecture Nehalem Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 VT-x, VT-d Physical specifications Transistors 731M to 2300M 45 nm Cores 2-6 (4-8 Xeon) Socket(s) LGA 1156 LGA 1366 LGA 1567 µPGA 988 Products, models, variants Model(s) Pentium, Core, Core in and Xeon Series History Predecessor Core (tock) Penryn (tick) Successor Westmere (tick) Sandy Bridge (tock) Support status Unsupported Westmere General information Launched January 7, 2010 (January 7, 2010) Performance Max. CPU clock rate 1.06 GHz to 3.46 GHz QPI speeds 4.80 GT/s to 6.40 GT/s DMI speeds 2.50 GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 MB to 30 MB shared Architecture and classification Microarchitecture Nehalem Instruction set x86-64 Instructions IA-32, x86-64 Extensions AES-NI, CLMUL MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 VT-x, VT-d Physical specifications Transistors 382M to 2600M 32nm Cores 2-6 (4-10 Xeon) GPU(s) 533 MHz to 900 MHz 177M 45nm (K0) Socket(s) LGA 1156 LGA 1366 LGA 1567 rPGA988A Products, models, variants Model(s) Core in, Xeon History Predecessor Nehalem Successor Sandy Bridge Support status Unsupported Sandy Bridge General information Launched January 9, 2011 (January 9, 2011) Discontinued September 27, 2013 Product code 80619 (extreme desktop) 80620 (server LGA1356) 80621 (server LGA2011) 80623 (desktop) 80627 (mobile) Performance Max. CPU clock rate 1.60 GHz to 3.60 GHz DMI speeds 5.00 GT/s GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 1 MB to 8 MB shared 10 MB to 15 MB (Extreme) 3 MB to 20 MB (Xeon) Architecture and classification Microarchitecture Sandy Bridge Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX VT-x, VT-d AES-NI, CLMUL, TXT Physical specifications Transistors 504M to 2.27B 32nm Cores 1–4 (4-6 Extreme, 2-8 Xeon) GPU(s) HD Graphics 650 MHz to 1100 MHz HD Graphics 2000 650 MHz to 1250 MHz HD Graphics 3000 650 MHz to 1350 MHz HD Graphics P3000 850 MHz to 1350 MHz Socket(s) LGA 1155 (desktops and workstations) LGA 2011 (high-end servers) LGA 1356 (low-end, dual-processor servers) Socket G2 BGA-1023 BGA-1224 BGA-1284 Products, models, variants Model(s) Celeron Series Pentium Series Core i3/i5/i7/i7 Extreme Series Xeon E3/E5 Series History Predecessor Nehalem (Tock) Westmere (Tick) Successor Ivy Bridge (Tick) Haswell (Tock) Support status Unsupported Ivy Bridge Intel's internal Ivy Bridge logo General information Launched April 29, 2012 (April 29, 2012) Discontinued June 5, 2015 (June 5, 2015) Marketed by Intel Designed by Intel Common manufacturer(s) Intel CPUID code 0306A9h Product code 80633 (extreme desktop) 80634 (server LGA1356) 80635 (server E5 LGA2011) 80636 (server E7 LGA2011) 80637 (desktop) 80638 (mobile) Performance Max. CPU clock rate 1.4 to 4.1 GHz DMI speeds 5.00 GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 to 8 MB shared Architecture and classification Technology node Intel 22 nm Microarchitecture Sandy Bridge Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, F16C AES-NI, CLMUL, RDRAND, TXT VT-x, VT-d Physical specifications Transistors 2.104B Cores 2–4 (Mainstream) 2–15 (Xeon) GPU(s) HD Graphics 2500 650 to 1150 MHz HD Graphics 4000 350 to 1300 MHz HD Graphics P4000 650 to 1250 MHz Socket(s) Desktop & Workstation LGA 1155 LGA 2011 Server LGA 2011 LGA 2011-1 LGA 1356 Mobile Socket G2 BGA 1023 BGA 1224 BGA 1284 Products, models, variants Model(s) Celeron G Series Pentium G Series Core i3 Series Core i5 Series Core i7 Series Xeon E3/E5/E7 v2 Series Brand name(s) Celeron Pentium Core Xeon History Predecessor Sandy Bridge (Tock) Successor Haswell (Tock/Architecture) Support status Unsupported Haswell A Haswell wafer with several dies, with a pin for scale General information Launched June 4, 2013 (June 4, 2013) CPUID code 0306C3h Product code 80646 (desktop LGA 1150) 80647 (mobile Socket G3) 80648 (desktop LGA 2011-3) 80644 (server LGA 2011-3) Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2–45 MB (shared) L4 cache 128 MB of eDRAM (Iris Pro models only) Architecture and classification Technology node 22 nm (Tri-Gate) Microarchitecture Haswell Instruction set x86-64 Instructions x86, x86-64 Extensions AES-NI, CLMUL, RDRAND, TXT MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, FMA3, AVX, AVX2, and TSX (disabled via microcode, except for Haswell-EX) VT-x, VT-d Physical specifications Cores 2–4 (mainstream) 6–8 (enthusiast) 2–18 (Xeon) GPU(s) HD Graphics 4200 HD Graphics 4400 HD Graphics 4600 HD Graphics 5000 Iris 5100 Iris Pro 5200 Socket(s) LGA 1150 rPGA 947 BGA 1364 BGA 1168 LGA 2011-v3 Products, models, variants Model(s) Haswell Haswell Refresh Haswell-E Haswell-EP Haswell-EX Brand name(s) Core i3 Core i5 Core i7 Xeon E3 v3 Xeon E5 v3 Xeon E7 v3 Pentium Celeron History Predecessor Sandy Bridge (Tock) Ivy Bridge (Tick) Successor Broadwell (Tick/Process) Skylake (Tock) Support status Unsupported Broadwell General information Launched October 27, 2014 (October 27, 2014) Discontinued November 2018 CPUID code 0306D4h Product code 80658 (mainstream desktop/mobile, Xeon E3) 80660 (Xeon E5) 80669 (Xeon E7) 80671 (enthusiast desktop) 80674 (Xeon D) 80682 (Xeon D, Hewitt Lake) Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2-6 MB (shared) L4 cache 128 MB of eDRAM (Iris Pro models only) Architecture and classification Technology node 14 nm (Tri-Gate) Microarchitecture Haswell Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, TSX, FMA3 AES-NI, CLMUL, RDRAND, TXT VT-x, VT-d Physical specifications Cores 2–4 (mainstream) 6–10 (enthusiast) 4–24 (Xeon) GPU(s) HD 5300 HD 5500 HD 5700P HD 6000 HD 6100 HD 6200 HD 6300P HD Graphics Socket(s) LGA 1150 BGA 1364 LGA 2011-v3 Products, models, variants Brand name(s) Core i3 Core i5 Core i7 Core M Celeron Pentium Xeon History Predecessor Haswell (Tock/Architecture) Haswell Refresh (Optimization) Successor Skylake (Tock/Architecture) Support status Unsupported Skylake Intel Core i7-6700K with four physical cores General information Launched August 5, 2015 (August 5, 2015) Discontinued March 4, 2019 (March 4, 2019) (desktop processors) Marketed by Intel Designed by Intel Common manufacturer(s) Intel CPUID code 0406e3h, 0506e3h Product code 80662 (mainstream and mobile Xeon E3) 80673 (enthusiast and server) Performance Max. CPU clock rate Up to 4.5 GHz Cache L1 cache 64 KB per core L2 cache 256 KB per core (1 MB per core for Skylake-X) L3 cache Up to 2 MB per core (1.375 MB per core for Skylake-X) L4 cache 128 MB of eDRAM (on select models) Architecture and classification Technology node 14 nm bulk silicon 3D transistors (Tri-Gate) Microarchitecture Skylake Instruction set x86-64 Instructions x86-64 (Intel 64) Extensions AES-NI, CLMUL, RDRAND, MPX, TXT, SGX MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, ADX AVX, AVX2, AVX-512 (SkyLake-SP, SkyLake-W & SkyLake-X), TSX, FMA3 VT-x, VT-d Physical specifications Cores 2–28 Socket(s) Desktop LGA 1151 LGA 2066 Server & Workstation LGA 3647 LGA 2066 Mobile BGA 1168 BGA 1356 BGA 1515 BGA 1440 Products, models, variants Brand name(s) Core i3 Core i5 Core i7 Core i9 Core m3 Core m5 Core m7 Xeon Celeron Pentium History Predecessor Broadwell (Tick/Process) Successor Kaby Lake (Optimization) Cascade Lake-SP (Skylake-SP) Palm Cove (Process) Support status Client: Legacy support for iGPU Xeon E3: Legacy support for iGPU Other Xeon: supported Cannon Lake General information Launched May 15, 2018 (May 15, 2018) Discontinued February 28, 2020 (February 28, 2020) Marketed by Intel Designed by Intel Common manufacturer(s) Intel Performance Max. CPU clock rate 3.2 GHz Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 MB per core Architecture and classification Technology node Intel 10 nm (tri-gate) transistors Microarchitecture Palm Cove Instruction set x86-64 Instructions x86-64, Intel 64 Extensions MMX, AES-NI, CLMUL, RDRAND, FMA3, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, SHA, TXT, TSX, SGX, VT-x, VT-d Physical specifications Cores 2 GPU(s) Factory disabled Socket(s) BGA 1440 Products, models, variants Brand name(s) Core History Predecessor Desktop: Coffee Lake (2nd optimization) Kaby Lake Refresh (2nd optimization) Successor Ice Lake (architecture) Support status Legacy support for iGPU Apple A11 Bionic General information Launched September 12, 2017 Discontinued present Designed by Apple Inc. Common manufacturer(s) TSMC Product code APL1W72 Max. CPU clock rate to 2.39 GHz  Cache L1 cache 32 KB instruction, 32 KB data L2 cache 8 MB L3 cache none Architecture and classification Application Mobile Technology node 10 nm Microarchitecture ARMv8‑A compatible Instruction set A64 Physical specifications Cores 6 GPU(s) Apple-designed 3 core Products, models, variants Core name(s) Monsoon Mistral Product code name(s) test1 History Predecessor Apple A10 Fusion

Testing main template {{Infobox CPU}} Infobox CPU/testcases An Intel A80286-8 processor with a gray ceramic heat spreader General information Launched February 1982 Discontinued 1991 Common manufacturer(s) Intel, IBM, AMD, Harris (Intersil), Siemens, Fujitsu Performance Max. CPU clock rate 4 MHz to 25 MHz FSB speeds 4 MHz to 25 MHz Data width 16 bits Address width 24 bits Architecture and classification Technology node 1.5 µm Instruction set x86-16 (with MMU) Physical specifications Transistors 120,000 or 134,000, 1.5µm Co-processor Intel 80287 Package(s) 68-pin PLCC 68-pin LCC 68-pin PGA 100-pin PQFP (engineering sample only) Socket(s) PGA68 PLCC-68 LCC-68 History Predecessor(s) 8086, 8088 (while 80186 was contemporary) Successor(s) Intel 80386 Support status Unsupported Pentium (i586) General information Launched March 22, 1993 Discontinued July 15, 1999 Performance Max. CPU clock rate 60–300 MHz FSB speeds 50–66 MHz Cache L1 cache 16–32 KiB Architecture and classification Microarchitecture P5 Instruction set IA-32 Extensions MMX Physical specifications Transistors 3.1M 0.8 μm (P5) 3.2M 0.6 μm (P54C) 3.3M 350 nm (P54CS) 4.5M 350 nm (P55C) Cores 1 Socket(s) Socket 4 Socket 5 Socket 7 Products, models, variants Model(s) Pentium series Pentium OverDrive series Pentium MMX series History Predecessor(s) i486 Successor(s) P6, Pentium II Support status Unsupported P6 Die shot of Deschutes core General information Launched November 1, 1995 (November 1, 1995) Performance Max. CPU clock rate 150 MHz to 1.40 GHz FSB speeds 66 MHz to 133 MHz Cache L1 cache Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache) Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache) L2 cache 128 KB to 512 KB 256 KB to 2048 KB (Xeon) Architecture and classification Microarchitecture P6 Instruction set x86 Extensions MMX (Pentium II/III) SSE (Pentium III) Physical specifications Transistors 5.5M 500 nm 7.5M 350 nm 7.5M 250 nm (B0, B1) 9.5M 250 nm (B0, C0) 19M 250 nm (B0) 28M 180 nm (A1, A2, B0, C0, D0) 44M 130 nm (A1, B1, C1, D0) Cores 1 Socket(s) Socket 8 Slot 1 Socket 370 Socket 479 Products, models, variants Model(s) Celeron Series Pentium II Series Pentium III Series Pentium Pro Series Pentium II Xeon Series Pentium III Xeon Series Variant(s) Pentium M Enhanced Pentium M History Predecessor(s) P5 Successor(s) NetBurst, Pentium M Support status Unsupported P6 Pentium M General information Launched March 12, 2003 Performance Max. CPU clock rate 600 MHz to 2.26 GHz FSB speeds 400 MT/s to 533 MT/s Cache L1 cache 64KB (32 KB I Cache + 32 KB D cache) L2 cache 512 KB to 2048 KB Architecture and classification Microarchitecture P6 Instruction set x86 Extensions MMX, SSE, SSE2 Physical specifications Transistors 77M 130 nm (B1, B2) 144M 90 nm (B0, C0) 151M 65 nm (C0, D0) Cores 1 Socket(s) Socket M Products, models, variants Model(s) A100 Series EP80579 Series Celeron M Series Pentium M Series History Predecessor(s) NetBurst Successor(s) Enhanced Pentium M Support status Unsupported P6 Enhanced Pentium M General information Launched 2006 Performance Max. CPU clock rate 1.06 GHz to 2.33 GHz FSB speeds 533 MT/s to 667 MT/s Cache L1 cache 64 KB L2 cache 1 MB to 2 MB 2 MB (Xeon) Architecture and classification Microarchitecture P6 Instruction set x86 Extensions MMX, SSE, SSE2, SSE3 Physical specifications Transistors 151M 65 nm (C0, D0) Cores 1-2 Socket(s) Socket M Products, models, variants Model(s) Celeron M Series Pentium Dual-Core Series Core Solo Series Core Duo Series Xeon LV Series History Predecessor(s) Pentium M Successor(s) Intel Core Support status Unsupported NetBurst General information Launched November 20, 2000 (November 20, 2000) Performance Max. CPU clock rate 1.3 GHz to 3.8 GHz FSB speeds 400 MT/s to 1066 MT/s Cache L1 cache 8 KB to 16 KB per core L2 cache 128 KB to 2048 KB L3 cache 4 MB to 16 MB shared Architecture and classification Microarchitecture NetBurst Instruction set x86 (IA-32), x86-64 (some) Extensions MMX, SSE, SSE2, SSE3 (some) Physical specifications Transistors 42M 180 nm (B2, C1, D0, E0) 55M 130 nm (B0, C1, D1, M0) 125M 90 nm (C0, D0, E0, G1) 169M 90 nm (M0, N0, R0) 230M 90 nm (A0, B0) 188M 65 nm (B1, C1, D0) 376M 65 nm (B1, C1, D0) 1,328M 65 nm (B0) Cores 1-2 (2-4 threads with HT) Socket(s) Socket 423 Socket 478 Socket 603 Socket 604 LGA 771 LGA 775 Products, models, variants Model(s) Celeron Series Celeron D Series Pentium 4 Series Pentium D Series Xeon Series History Predecessor(s) P6 Successor(s) Intel Core IA-64 Intel Core General information Launched June 26, 2006 (June 26, 2006) (Xeon) July 27, 2006 (July 27, 2006) (Core 2) Performance Max. CPU clock rate 933 MHz to 3.5 GHz FSB speeds 533 MT/s to 1600 MT/s Cache L1 cache 64 KB per core L2 cache 0.5 to 6 MB per two cores L3 cache 8 MB to 16 MB shared (Xeon 7400) Architecture and classification Technology node 65 nm to 45 nm Microarchitecture Core Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4 (45nm Core 2 only), VT-x (some) Physical specifications Transistors 105M to 582M (65 nm) 228M to 1900M (45 nm) Cores 1–4 (2-6 Xeon) Socket(s) Socket M (µPGA 478) Socket P (µPGA 478) Socket T (LGA 775) Socket J (LGA 771) Socket 604 FCBGA (µBGA 479) FCBGA (µBGA 965) Products, models, variants Model(s) P6 family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon) History Predecessor(s) NetBurst Enhanced Pentium M (P6) Successor(s) Penryn (tick) (a version of Core) Nehalem (tock) Support status Unsupported Penryn General information Launched November 2007 (November 2007) Performance Max. CPU clock rate 1.06 GHz to 3.33 GHz FSB speeds 533 MT/s to 1600 MT/s Cache L1 cache 64 KB per core L2 cache 1 MB to 12 MB unified L3 cache 8 MB to 16 MB shared (Xeon) Architecture and classification Microarchitecture Core Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1 VT-x, VT-d Physical specifications Transistors 228M to 820M 45 nm Cores 1-4 (2-6 Xeon) Socket(s) Socket M (µPGA 478) Socket P (µPGA 478) Socket T (LGA 775) FCBGA (μBGA 479) FCBGA (μBGA 965) Products, models, variants Model(s) P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon) History Predecessor(s) Core Successor(s) Nehalem Support status Unsupported Nehalem General information Launched November 11, 2008 (November 11, 2008) Performance Max. CPU clock rate 1.06 GHz to 3.33 GHz QPI speeds 4.80 GT/s to 6.40 GT/s DMI speeds 2.50 GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 MB to 24 MB shared Architecture and classification Technology node 45 nm Microarchitecture Nehalem Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 VT-x, VT-d Physical specifications Transistors 731M to 2300M 45 nm Cores 2-6 (4-8 Xeon) Socket(s) LGA 1156 LGA 1366 LGA 1567 µPGA 988 Products, models, variants Model(s) Pentium, Core, Core in and Xeon Series History Predecessor(s) Core (tock) Penryn (tick) Successor(s) Westmere (tick) Sandy Bridge (tock) Support status Unsupported Westmere General information Launched January 7, 2010 (January 7, 2010) Performance Max. CPU clock rate 1.06 GHz to 3.46 GHz QPI speeds 4.80 GT/s to 6.40 GT/s DMI speeds 2.50 GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 MB to 30 MB shared Architecture and classification Microarchitecture Nehalem Instruction set x86-64 Instructions IA-32, x86-64 Extensions AES-NI, CLMUL MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 VT-x, VT-d Physical specifications Transistors 382M to 2600M 32nm Cores 2-6 (4-10 Xeon) GPU(s) 533 MHz to 900 MHz 177M 45nm (K0) Socket(s) LGA 1156 LGA 1366 LGA 1567 rPGA988A Products, models, variants Model(s) Core in, Xeon History Predecessor(s) Nehalem Successor(s) Sandy Bridge Support status Unsupported Sandy Bridge General information Launched January 9, 2011 (January 9, 2011) Discontinued September 27, 2013 Product code 80619 (extreme desktop) 80620 (server LGA1356) 80621 (server LGA2011) 80623 (desktop) 80627 (mobile) Performance Max. CPU clock rate 1.60 GHz to 3.60 GHz DMI speeds 5.00 GT/s GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 1 MB to 8 MB shared 10 MB to 15 MB (Extreme) 3 MB to 20 MB (Xeon) Architecture and classification Microarchitecture Sandy Bridge Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX VT-x, VT-d AES-NI, CLMUL, TXT Physical specifications Transistors 504M to 2.27B 32nm Cores 1–4 (4-6 Extreme, 2-8 Xeon) GPU(s) HD Graphics 650 MHz to 1100 MHz HD Graphics 2000 650 MHz to 1250 MHz HD Graphics 3000 650 MHz to 1350 MHz HD Graphics P3000 850 MHz to 1350 MHz Socket(s) LGA 1155 (desktops and workstations) LGA 2011 (high-end servers) LGA 1356 (low-end, dual-processor servers) Socket G2 BGA-1023 BGA-1224 BGA-1284 Products, models, variants Model(s) Celeron Series Pentium Series Core i3/i5/i7/i7 Extreme Series Xeon E3/E5 Series History Predecessor(s) Nehalem (Tock) Westmere (Tick) Successor(s) Ivy Bridge (Tick) Haswell (Tock) Support status Unsupported Ivy Bridge Intel's internal Ivy Bridge logo General information Launched April 29, 2012 (April 29, 2012) Discontinued June 5, 2015 (June 5, 2015) Marketed by Intel Designed by Intel Common manufacturer(s) Intel CPUID code 0306A9h Product code 80633 (extreme desktop) 80634 (server LGA1356) 80635 (server E5 LGA2011) 80636 (server E7 LGA2011) 80637 (desktop) 80638 (mobile) Performance Max. CPU clock rate 1.4 to 4.1 GHz DMI speeds 5.00 GT/s Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 to 8 MB shared Architecture and classification Technology node Intel 22 nm Microarchitecture Sandy Bridge Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, F16C AES-NI, CLMUL, RDRAND, TXT VT-x, VT-d Physical specifications Transistors 2.104B Cores 2–4 (Mainstream) 2–15 (Xeon) GPU(s) HD Graphics 2500 650 to 1150 MHz HD Graphics 4000 350 to 1300 MHz HD Graphics P4000 650 to 1250 MHz Socket(s) Desktop & Workstation LGA 1155 LGA 2011 Server LGA 2011 LGA 2011-1 LGA 1356 Mobile Socket G2 BGA 1023 BGA 1224 BGA 1284 Products, models, variants Model(s) Celeron G Series Pentium G Series Core i3 Series Core i5 Series Core i7 Series Xeon E3/E5/E7 v2 Series Brand name(s) Celeron Pentium Core Xeon History Predecessor(s) Sandy Bridge (Tock) Successor(s) Haswell (Tock/Architecture) Support status Unsupported Haswell A Haswell wafer with several dies, with a pin for scale General information Launched June 4, 2013 (June 4, 2013) CPUID code 0306C3h Product code 80646 (desktop LGA 1150) 80647 (mobile Socket G3) 80648 (desktop LGA 2011-3) 80644 (server LGA 2011-3) Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2–45 MB (shared) L4 cache 128 MB of eDRAM (Iris Pro models only) Architecture and classification Technology node 22 nm (Tri-Gate) Microarchitecture Haswell Instruction set x86-64 Instructions x86, x86-64 Extensions AES-NI, CLMUL, RDRAND, TXT MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, FMA3, AVX, AVX2, and TSX (disabled via microcode, except for Haswell-EX) VT-x, VT-d Physical specifications Cores 2–4 (mainstream) 6–8 (enthusiast) 2–18 (Xeon) GPU(s) HD Graphics 4200 HD Graphics 4400 HD Graphics 4600 HD Graphics 5000 Iris 5100 Iris Pro 5200 Socket(s) LGA 1150 rPGA 947 BGA 1364 BGA 1168 LGA 2011-v3 Products, models, variants Model(s) Haswell Haswell Refresh Haswell-E Haswell-EP Haswell-EX Brand name(s) Core i3 Core i5 Core i7 Xeon E3 v3 Xeon E5 v3 Xeon E7 v3 Pentium Celeron History Predecessor(s) Sandy Bridge (Tock) Ivy Bridge (Tick) Successor(s) Broadwell (Tick/Process) Skylake (Tock) Support status Unsupported Broadwell General information Launched October 27, 2014 (October 27, 2014) Discontinued November 2018 CPUID code 0306D4h Product code 80658 (mainstream desktop/mobile, Xeon E3) 80660 (Xeon E5) 80669 (Xeon E7) 80671 (enthusiast desktop) 80674 (Xeon D) 80682 (Xeon D, Hewitt Lake) Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2-6 MB (shared) L4 cache 128 MB of eDRAM (Iris Pro models only) Architecture and classification Technology node 14 nm (Tri-Gate) Microarchitecture Haswell Instruction set x86-64 Instructions x86, x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, TSX, FMA3 AES-NI, CLMUL, RDRAND, TXT VT-x, VT-d Physical specifications Cores 2–4 (mainstream) 6–10 (enthusiast) 4–24 (Xeon) GPU(s) HD 5300 HD 5500 HD 5700P HD 6000 HD 6100 HD 6200 HD 6300P HD Graphics Socket(s) LGA 1150 BGA 1364 LGA 2011-v3 Products, models, variants Brand name(s) Core i3 Core i5 Core i7 Core M Celeron Pentium Xeon History Predecessor(s) Haswell (Tock/Architecture) Haswell Refresh (Optimization) Successor(s) Skylake (Tock/Architecture) Support status Unsupported Skylake Intel Core i7-6700K with four physical cores General information Launched August 5, 2015 (August 5, 2015) Discontinued March 4, 2019 (March 4, 2019) (desktop processors) Marketed by Intel Designed by Intel Common manufacturer(s) Intel CPUID code 0406e3h, 0506e3h Product code 80662 (mainstream and mobile Xeon E3) 80673 (enthusiast and server) Performance Max. CPU clock rate Up to 4.5 GHz Cache L1 cache 64 KB per core L2 cache 256 KB per core (1 MB per core for Skylake-X) L3 cache Up to 2 MB per core (1.375 MB per core for Skylake-X) L4 cache 128 MB of eDRAM (on select models) Architecture and classification Technology node 14 nm bulk silicon 3D transistors (Tri-Gate) Microarchitecture Skylake Instruction set x86-64 Instructions x86-64 (Intel 64) Extensions AES-NI, CLMUL, RDRAND, MPX, TXT, SGX MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, ADX AVX, AVX2, AVX-512 (SkyLake-SP, SkyLake-W & SkyLake-X), TSX, FMA3 VT-x, VT-d Physical specifications Cores 2–28 Socket(s) Desktop LGA 1151 LGA 2066 Server & Workstation LGA 3647 LGA 2066 Mobile BGA 1168 BGA 1356 BGA 1515 BGA 1440 Products, models, variants Brand name(s) Core i3 Core i5 Core i7 Core i9 Core m3 Core m5 Core m7 Xeon Celeron Pentium History Predecessor(s) Broadwell (Tick/Process) Successor(s) Kaby Lake (Optimization) Cascade Lake-SP (Skylake-SP) Palm Cove (Process) Support status Client: Legacy support for iGPU Xeon E3: Legacy support for iGPU Other Xeon: supported Cannon Lake General information Launched May 15, 2018 (May 15, 2018) Discontinued February 28, 2020 (February 28, 2020) Marketed by Intel Designed by Intel Common manufacturer(s) Intel Performance Max. CPU clock rate 3.2 GHz Cache L1 cache 64 KB per core L2 cache 256 KB per core L3 cache 2 MB per core Architecture and classification Technology node Intel 10 nm (tri-gate) transistors Microarchitecture Palm Cove Instruction set x86-64 Instructions x86-64, Intel 64 Extensions MMX, AES-NI, CLMUL, RDRAND, FMA3, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, SHA, TXT, TSX, SGX, VT-x, VT-d Physical specifications Cores 2 GPU(s) Factory disabled Socket(s) BGA 1440 Products, models, variants Brand name(s) Core History Predecessor(s) Desktop: Coffee Lake (2nd optimization) Kaby Lake Refresh (2nd optimization) Successor(s) Ice Lake (architecture) Support status Legacy support for iGPU