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For other uses, see SPARC (disambiguation).
SPARC
DesignerSun Microsystems (owned by Oracle Corporation)
Bits64-bit (32 → 64)
Introduced1987 (shipments)
VersionV9 (1993)
DesignRISC
TypeRegister-Register
EncodingFixed
BranchingCondition code
EndiannessBi (Big → Bi)
Page size8 KiB
ExtensionsVIS 1.0, 2.0, 3.0
OpenYes
Registers
General-purpose31 (G0 = 0; non-global registers use register windows)
Floating point32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)
Sun UltraSPARC II Microprocessor

SPARC (from Scalable Processor Architecture) is a RISC instruction set architecture (ISA) developed by Sun Microsystems and introduced in mid-1987.

SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Implementations of the original 32-bit SPARC architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMP servers produced by Sun Microsystems, Solbourne and Fujitsu, among others, and designed for 64-bit operation.

SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Atmel, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

In March 2006 the complete design of Sun Microsystems' UltraSPARC T1 microprocessor was released in open-source form at OpenSPARC.net and named the OpenSPARC T1. In 2007 the design of Sun's UltraSPARC T2 microprocessor was also released in open-source form as OpenSPARC T2.[1]

The most recent commercial iterations of the SPARC processor design are the Fujitsu Laboratories Ltd.'s "Venus" 128 GFLOP SPARC64 VIIIfx introduced June 2009, which is used in the 8 petaFLOPS Japanese supercomputer "K computer", and the SPARC T4 introduced by Oracle Corporation in September 2011; both are 8 core devices running at 2.0GHz and over 2.5GHz respectively.

Features

The SPARC architecture was heavily influenced by the earlier RISC designs including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 160 general purpose registers. At any point, only 32 of them are immediately visible to software - 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.[2][3] 64-bit (addressing and data) were added to the version 9 SPARC specification published in 1994.[4]

In SPARC Version 8, the floating point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers.

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

History

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VIS 1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1 implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification.

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

The SPARC architecture has been licensed to many companies who have developed and fabricated implementations such as:

SPARC microprocessor specifications

This table contains specifications for certain SPARC processors: frequency (megahertz), architecture version, release year, number of threads (threads per core multiplied by the number of cores), fabrication process (micrometers), number of transistors (millions), die size (square millimetres), number of I/O pins, dissipated power (watts), voltage, and cache sizes—data, instruction, L2 and L3 (kibibytes).

Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (µm) Transistors (millions) Die size (mm²) IO Pins Power (W) Voltage (V) L1 Dcache (KiB) L1 Icache (KiB) L2 Cache (KiB) L3 Cache (KiB)
SPARC (various), including MB86900[note 2] 14.28–40 V7 1987–1992 1×1=1 0.8–1.3 ~0.1–1.8 -- 160–256 -- -- 0–128 (unified) none none
microSPARC I (Tsunami) TI TMS390S10 40–50 V8 1992 1×1=1 0.8 0.8 225? 288 2.5 5 2 4 none none
SuperSPARC I (Viking) TI TMX390Z50 / Sun STP1020 33–60 V8 1992 1×1=1 0.8 3.1 -- 293 14.3 5 16 20 0-2048 none
SPARClite Fujitsu MB8683x 66–108 V8E 1992 1×1=1 -- -- -- 144, 176 -- 2.5/3.3V-5.0V, 2.5V-3.3V 1, 2, 8, 16 1, 2, 8, 16 none none
hyperSPARC (Colorado 1) Ross RT620A 40–90 V8 1993 1×1=1 0.5 1.5 -- -- -- 5? 0 8 128-256 none
microSPARC II (Swift) Fujitsu MB86904 / Sun STP1012 60–125 V8 1994 1×1=1 0.5 2.3 233 321 5 3.3 8 16 none none
hyperSPARC (Colorado 2) Ross RT620B 90–125 V8 1994 1×1=1 0.4 1.5 -- -- -- 3.3 0 8 128-256 none
SuperSPARC II (Voyager) Sun STP1021 75–90 V8 1994 1×1=1 0.8 3.1 299 -- 16 -- 16 20 1024-2048 none
hyperSPARC (Colorado 3) Ross RT620C 125–166 V8 1995 1×1=1 0.35 1.5 -- -- -- 3.3 0 8 512-1024 none
TurboSPARC Fujitsu MB86907 160–180 V8 1996 1×1=1 0.35 3.0 132 416 7 3.5 16 16 512 none
UltraSPARC (Spitfire) Sun STP1030 143–167 V9 1995 1×1=1 0.47 5.2 315 521 30[note 3] 3.3 16 16 512-1024 none
UltraSPARC (Hornet) Sun STP1030 200 V9 1998 1×1=1 0.42 5.2 265 521 -- 3.3 16 16 512-1024 none
hyperSPARC (Colorado 4) Ross RT620D 180–200 V8 1996 1×1=1 0.35 1.7 -- -- -- 3.3 16 16 512 none
SPARC64 Fujitsu (HAL) 101–118 V9 1995 1×1=1 0.4 -- Multichip 286 50 3.8 128 128 -- --
SPARC64 II Fujitsu (HAL) 141–161 V9 1996 1×1=1 0.35 -- Multichip 286 64 3.3 128 128 -- --
SPARC64 III Fujitsu (HAL) MBCS70301 250–330 V9 1998 1×1=1 0.24 17.6 240 -- -- 2.5 64 64 8192 --
UltraSPARC IIs (Blackbird) Sun STP1031 250–400 V9 1997 1×1=1 0.35 5.4 149 521 25[note 4] 2.5 16 16 1024 or 4096 none
UltraSPARC IIs (Sapphire-Black) Sun STP1032 / STP1034 360–480 V9 1999 1×1=1 0.25 5.4 126 521 21[note 5] 1.9 16 16 1024–8192 none
UltraSPARC IIi (Sabre) Sun SME1040 270–360 V9 1997 1×1=1 0.35 5.4 156 587 21 1.9 16 16 256–2048 none
UltraSPARC IIi (Sapphire-Red) Sun SME1430 333–480 V9 1998 1×1=1 0.25 5.4 -- 587 21[note 6] 1.9 16 16 2048 none
UltraSPARC IIe (Hummingbird) Sun SME1701 400–500 V9 1999 1×1=1 0.18 Al -- -- 370 13[note 7] 1.5-1.7 16 16 256 none
UltraSPARC IIi (IIe+) (Phantom) Sun SME1532 550–650 V9 2000 1×1=1 0.18 Cu -- -- 370 17.6 1.7 16 16 512 none
SPARC64 GP Fujitsu SFCB81147 400–563 V9 2000 1×1=1 0.18 30.2 217 -- -- 1.8 128 128 8192 --
SPARC64 GP -- 600–810 V9 -- 1×1=1 0.15 30.2 -- -- -- 1.5 128 128 8192 --
SPARC64 IV Fujitsu MBCS80523 450–810 V9 2000 1×1=1 0.13 -- -- -- -- -- 128 128 2048 --
UltraSPARC III (Cheetah) Sun SME1050 600 V9 / JPS1 2001 1×1=1 0.18 Al 29 330 1368 53 1.6 64 32 8192 none
UltraSPARC III (Cheetah) Sun SME1052 750–900 V9 / JPS1 2001 1×1=1 0.13 Al 29 -- 1368 -- 1.6 64 32 8192 none
UltraSPARC III Cu (Cheetah+) Sun SME1056 1002–1200 V9 / JPS1 2001 1×1=1 0.13 Cu 29 232 1368 80[note 8] 1.6 64 32 8192 none
UltraSPARC IIIi (Jalapeño) Sun SME1603 1064–1593 V9 / JPS1 2003 1×1=1 0.13 87.5 206 959 52 1.3 64 32 1024 none
SPARC64 V (Zeus) Fujitsu 1100–1350 V9 / JPS1 2003 1×1=1 0.13 190 289 269 40 1.2 128 128 2048 --
SPARC64 V+ (Olympus-B) Fujitsu 1650–2160 V9 / JPS1 2004 1×1=1 0.09 400 297 279 65 1 128 128 4096 --
UltraSPARC IV (Jaguar) Sun SME1167 1050–1350 V9 / JPS1 2004 1×2=2 0.13 66 356 1368 108 1.35 64 32 16384 none
UltraSPARC IV+ (Panther) Sun SME1167A 1500–2100 V9 / JPS1 2005 1×2=2 0.09 295 336 1368 90 1.1 64 64 2048 32768
UltraSPARC T1 (Niagara) Sun SME1905 1000–1400 V9 / UA 2005 2005 4×8=32 0.09 300 340 1933 72 1.3 8 16 3072 none
SPARC64 VI (Olympus-C) Fujitsu 2150–2400 V9 / JPS1 2007 2×2=4 0.09 540 422 -- 120 -- 128x2 128x2 6144 none
UltraSPARC T2 (Niagara 2) Sun SME1908A 1000–1600 V9 / UA 2007 2007 8×8=64 0.065 503 342 1831 95 1.1–1.5 8 16 4096 none
UltraSPARC T2 Plus (Victoria Falls) Sun SME1910A 1200–1600 V9 / UA 2007 2008 8×8=64 0.065 503 342 1831 - - 8 16 4096 none
SPARC64 VII (Jupiter) [5] Fujitsu 2400–2880 V9 / JPS1 2008 2×4=8 0.065 600 445 -- 150 -- 64x4 64x4 6144 none
UltraSPARC "RK" (Rock)[6] Sun SME1832 2300 V9 / -- canceled[7] 2×16=32 0.065 ? 396 2326 ? ? 32 32 2048 ?
SPARC64 VIIIfx (Venus)[8][9] Fujitsu 2000 V9 / JPS1 2009 1x8=8 0.045 760 513 1271 58 ? 32x8 32x8 6144 none
SPARC T3 (Rainbow Falls) Oracle/Sun 1650 V9 / UA _?_ 2010 8×16=128 0.040[10] ???? 371 ? 139 ? 8 16 6144 none
SPARC64 VII+ (Jupiter-E or M3)[11][12] Fujitsu 2667 - 3000 V9 / JPS1 2010 2x4=8 0.065 - - - 160 - 64x4 64x4 12288 none
MCST-4R MCST (Russia) 750 - 1000 V9 2010 1x4=4 0.09 150 115 - 15 1 32 16 2048 none
SPARC T4 (Yosemite Falls)[13] Oracle 2850 - 3000 V9 / OSA2011? 2011 8×8=64 0.04 855 403 ? 240 ? 16x8 16x8 128x8 4096
SPARC64 IXfx[14][15] Fujitsu 1850 V9 / JPS1? 2012 1x16=16 0.04 1870 484 1442 110 ? 32x16 32x16 12288 none
Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (µm) Transistors (millions) Die size (mm²) IO Pins Power (W) Voltage (V) L1 Dcache (k) L1 Icache (k) L2 Cache (k) L3 Cache (k)

Notes:

  1. ^ a b Threads per core × number of cores
  2. ^ Various SPARC V7 implementations were produced by Fujitsu, LSI Logic, Weitek, Texas Instruments and Cypress. A SPARC V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a floating-point unit (FPU), a memory management unit (MMU) and cache memory.
  3. ^ @167 MHz
  4. ^ @250 MHz
  5. ^ @400 MHz
  6. ^ @440 MHz
  7. ^ max@500 MHz
  8. ^ @900 MHz

Operating system support

SPARC machines have generally used Sun's SunOS, Solaris or OpenSolaris, but other operating systems such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux have also been used.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,[16] but it was later cancelled.

Open source implementations

Three fully open source implementations of the SPARC architecture exist:

  • LEON, a 32-bit, SPARC Version 8 implementation, designed especially for space use. Source code is written in VHDL, and licensed under the GPL.
  • OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary software license agreement.
    • S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC v9 core capable of 4 way SMT. Like the T1, the source code is licensed under the GPL.
  • OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.

A fully open source simulator for the SPARC architecture also exists:

  • RAMP Gold, a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of Systemverilog, and licensed under the BSD licenses.

Supercomputers

As of June 2011, only two supercomputers (#1 and #73) using SPARC microprocessors are included in the world's top 500 fastest supercomputers according to the TOP500 list. [17]

Fujitsu's K computer ranked #1 in Top500 - June 2011 and Nov 2011 lists.[17] It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the TOP500. The K Computer is more powerful than the next five systems on the list combined, and has the highest performance-to-power ratio of any current supercomputer system. It also ranked #6 in Green500 - June 2011 list, with a score of 824.56 MFLOPS/W.[18]

Tianhe-1A (currently #2) has a number of nodes with FeiTeng-1000 SPARC-based processors developed in China (based on OpenSPARC). However, those processors did not contribute to the LINPACK score.[19][20]

On Dec. 2, 2010, Oracle unveiled the SPARC SuperCluster with T3-2, T3-4 and M5000 servers.[21] The configuration with T3-4 servers was claimed to surpass the HP Integrity Superdome and the IBM Power 780 server, reaching speeds of 30,249,688 tpmC.[22]

See also

  • ERC32 – based on SPARC V7 specification
  • FeiTeng-1000 – A Chinese eight core Sparc based processor
  • MCST-4R – A Russian quad-core microprocessor based on SPARC V9 specification
  • OpenSPARC – an open source project based on the UltraSPARC T1 design
  • Rock processor – A multicore and multithread microprocessor with an emphasis on floating-point performance
  • Ross Technology, Inc. – A SPARC microprocessor developer during the 1980s and 1990s
  • Sparcle – modified SPARC with multiprocessing support used by the MIT Alewife project
  • UltraSPARC T1 – Sun's first multicore and multithread CPU (code-named "Niagara")
  • UltraSPARC T2 – The successor to T1
  • SPARC T3 – The successor to UltraSPARC T2

References

  1. ^ "OpenSPARC T2", OpenSPARC, Oracle Corporation, retrieved 2011-11-06
  2. ^ http://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html "integer multiply and integer divide instructions which exist in SPARC-V8 but not in SPARC-V7. "
  3. ^ http://www.osnews.com/story/6136 "The V8 architecture adds some instructions .., including integer divide and multiply."
  4. ^ Weaver, D. L.; Germond, T., eds. (1994), "The SPARC Architecture Manual, Version 9" (PDF), SPARC International, Inc., Prentice Hall, ISBN 0-13-825001-4, retrieved 2011-12-06
  5. ^ FX1 Key Features & Specifications (PDF), Fujitsu, 2008-02-19, retrieved 2011-12-06
  6. ^ Tremblay, Marc; Chaudhry, Shailender (2008-02-19), "A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC(R) Processor" (PDF), OpenSPARC, Sun Microsystems, retrieved 2011-12-06
  7. ^ Vance, Ashlee (2009-06-15), "Sun Is Said to Cancel Big Chip Project", The New York Times, retrieved 2010-05-23
  8. ^ "Fujitsu shows off SPARC64 VII", heise online, 2008-08-28, retrieved 2011-12-06
  9. ^ Barak, Sylvie (2009-05-14), "Fujitsu unveils world's fastest CPU", The Inquirer, retrieved 2011-12-06
  10. ^ "Sparc T3 processor" (PDF), Oracle Corporation, retrieved 2011-12-06
  11. ^ Morgan, Timothy Prickett (2010-12-03), "Ellison: Sparc T4 due next year", The Register, retrieved 2011-12-06
  12. ^ "SPARC Enterprise M-series Servers Architecture" (PDF), Fujitsu, 2011 {{citation}}: Unknown parameter |month= ignored (help)
  13. ^ Morgan, Timothy Prickett (2011-08-22), "Oracle's Sparc T4 chip", The Register, retrieved 2011-12-06
  14. ^ Morgan, Timothy Prickett (2011-11-21), "Fujitsu parades 16-core Sparc64 super stunner", The Register, retrieved 2011-12-08
  15. ^ "Fujitsu Launches PRIMEHPC FX10 Supercomputer", Fujitsu, 2011-11-07, retrieved 2012-02-03
  16. ^ McLaughlin, John (1993-07-07), "Intergraph to Port Windows NT to SPARC", The Florida SunFlash, 55 (11), retrieved 2011-12-06 {{citation}}: Check |authorlink= value (help)
  17. ^ a b "TOP500 List (1-100)", TOP500, 2011, retrieved 2011-12-06 {{citation}}: Unknown parameter |month= ignored (help)
  18. ^ "The Green500 List", Green500, 2011 {{citation}}: Unknown parameter |month= ignored (help)
  19. ^ Keane, Andy, "Tesla Supercomputing" (mp4), Nvidia, retrieved 2011-12-06
  20. ^ U.S. says China building 'entirely indigenous' supercomputer, by Patrick Thibodeau Computerworld, November 4, 2010 [1]
  21. ^ "Oracle Announces New SPARC Supercluster", Oracle, 2010-12-02, retrieved 2011-12-06
  22. ^ "Oracle Beats IBM with Nearly Three Times Better Throughput", Oracle, 2010-12-02, retrieved 2011-12-06
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