Cannon Lake (microprocessor)
 | This article needs additional citations for verification. (August 2012) |
| General information | |
|---|---|
| Launched | 2016 |
| Architecture and classification | |
| Instructions | MMX, AES-NI, CLMUL, FMA3 |
| Extensions | |
| Physical specifications | |
| Transistors | |
| Products, models, variants | |
| Model |
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| History | |
| Predecessor | Skylake |
In keeping with Intel's tick-tock principle, the 10 nm shrink of Skylake is due out the year after the introduction of the microarchitecture and is rumored to be codenamed "Skymont "; however no official announcement has been made. Further nodes are not clear either although latest Intel development (Q3 2012) indicates 7 nm node may reach production around 2017, with 5 nm in 2019.[1]
In 2009 Intel CEO Paul S. Otellini has been quoted as saying that silicon is in its last decade as the base material of the CPU.[2]
See also
- P5 (microarchitecture)
- P6 (microarchitecture)
- NetBurst (microarchitecture)
- Core (microarchitecture)
- Penryn (microarchitecture)
- Bonnell (microarchitecture)
- Nehalem (microarchitecture)
- Westmere (microarchitecture)
- Sandy Bridge (microarchitecture)
- Ivy Bridge (microarchitecture)
- Haswell (microarchitecture)
- Broadwell (microarchitecture)
- Silvermont (microarchitecture)
- Skylake (microarchitecture)
Roadmap
References
- ^ "Intel Has 5 nm Processors in Sight". tomshardware.com. Retrieved 2012-09-14.
- ^ "Intel looks beyond silicon for processors past 2017". Apcmag.com. Retrieved 2012-08-24.