Tiger Lake (microarchitecture)

Tiger Lake
Architecture and classification
Architecture	x86-64
Instructions	x86-64, Intel 64
Extensions	MMX, AES-NI, CLMUL, FMA3 SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 AVX, AVX2, AVX-512, SHA, TXT, TSX, SGX VT-x, VT-d
Physical specifications
Transistors	10 nm transistors
History
Predecessor	Ice Lake (Architecture)
Successor	Sapphire Rapids (unknown)

Tiger Lake is an Intel CPU microarchitecture based on the third-generation 10 nm process node (named "10nm++").^[1] It will replace Ice Lake.^[2] It's representing the Optimization step in Intel's Process-Architecture-Optimization model

Tiger Lake is slated to include quad-core 9W TDP and 25W TDP models.^[3] It will power some 2020 "Project Athena" laptops.^[4]

Features[edit]

Intel Willow Cove CPU cores (big core design).
The performance of Willow Cove is forecasted to be up to 30% increase clock for clock compare to Sunny Cove.
L1 instruction cache increase to 48KiB (12 way associativity, up from 32KiB) and data cache remain 48KiB (12 way associativity), L2 cache increase to 1.25MiB per core (20 way associativity, up from 512KiB 8 way associativity), 3MiB L3 cache per core.
L1 cache line increase to 128 bytes (up from 64 bytes since the Pentium 4 era), L2/L3 cache line increase to 256 bytes (up from 128 bytes since Core 2 Duo release)
Instruction fetch line increase from 16 bytes to 32 bytes, increase instruction decoder up to six (up from 4 way decoding since Core 2 Duo).
L4 cache will be reintroduced with HBM technology on some mobile model SKU and size can be up to 2GB.
Desktop SKU will have separate PCI Express controller design and move it back to its Platform Controller Hub (PCH).
Intel Xe ("Gen12") GPU with up to 96 execution units^[5]
Latest Display Technology
Next Gen I/O Technology
PCIe Gen 4 Support

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Discontinued
BCD oriented (4-bit)	4004 (1971) 4040 (1974)
pre-x86 (8-bit)	8008 (1972) 8080 (1974) 8085 (1977)
Early x86 (16-bit)	8086 (1978) 8088 (1979) 80186 (1982) 80188 (1982) 80286 (1982)
x87 (external FPUs)	8/16-bit databus 8087 (1980) 16-bit databus 80187 80287 80387SX 32-bit databus 80387DX 80487
IA-32 (32-bit)	80386 SX 376 EX 80486 SX DX2 DX4 SL RapidCAD OverDrive A100/A110 Celeron (1998) M D (2004) Pentium Original P5 OverDrive Pro II II OverDrive III 4 M Dual-Core some Core Solo Duo Tolapai
x86-64 (64-bit)	Celeron D Dual-Core Pentium 4 D Extreme Edition Dual-Core some Core 2 some i7
Other	CISC iAPX 432 RISC i860 i960 StrongARM XScale

Current
IA-32 (32-bit)	Atom CE SoC Quark
x86-64 (64-bit)	Atom CE SoC Celeron Pentium Core i3 i5 i7 i9 M Xeon E3 E5 E7 D Phi
EPIC	Itanium

Lists
Celeron Pentium Pro II III 4 D M Core Core 2 i3 i5 i7 i9 M Atom Xeon Itanium

Related
Tick–tock model Chipsets GPUs GMA HD and Iris Graphics PCHs SCHs ICHs PIIXs Stratix Codenames

P5	800 nm P5 600 nm P54C 350 nm P54CS P55C 250 nm Tillamook
P6, Pentium M, Enhanced Pentium M	500 nm P6 350 nm P6 Klamath 250 nm Mendocino Dixon Tonga Covington Deschutes Katmai Drake Tanner 180 nm Coppermine Coppermine T Timna Cascades 130 nm Tualatin Banias 90 nm Dothan Stealey Tolapai Canmore 65 nm Yonah Sossaman
NetBurst	180 nm Willamette Foster 130 nm Northwood Gallatin Prestonia 90 nm Tejas and Jayhawk Prescott Smithfield Nocona Irwindale Cranford Potomac Paxville 65 nm Cedar Mill Presler Dempsey Tulsa
Core	65 nm Merom-L Merom Conroe-L Allendale Conroe Kentsfield Woodcrest Clovertown Tigerton 45 nm Penryn Penryn-QC Wolfdale Yorkfield Wolfdale-DP Harpertown Dunnington
Nehalem	45 nm Auburndale Beckton (Nehalem-EX) Bloomfield Clarksfield Gainestown (Nehalem-EP) Havendale Jasper Forest Lynnfield 32 nm Arrandale Clarkdale Gulftown (Westmere-EP) Westmere-EX
Sandy Bridge	32 nm Sandy Bridge Sandy Bridge-E Gladden 22 nm Ivy Bridge Ivy Bridge-EP Ivy Bridge-EX
Haswell	22 nm Haswell 14 nm Broadwell
Skylake	14 nm Skylake Kaby Lake (Amber Lake) Coffee Lake Whiskey Lake Cascade Lake Comet Lake Cooper Lake 10 nm Cannon Lake
Sunny Cove	10 nm Ice Lake
Future	10 nm Tiger Lake 7 nm or 10 nm Sapphire Rapids Intel Xe (GPGPU)

Bonnell Saltwell	45 nm Silverthorne Diamondville Pineview Lincroft Tunnel Creek Stellarton Sodaville Groveland 32 nm Cedarview Penwell Cloverview Berryville Centerton
Silvermont Airmont	22 nm Valleyview Tangier Anniedale 14 nm Cherryview
Goldmont	14 nm Goldmont Goldmont Plus

Intel CPU core roadmaps from P6 to Tiger Lake

Microarchi.	Step	Feature size	Microarchi.	Step
Atom (ULV)		Feature size	x86
		600 nm	P6	Pentium Pro (133 MHz)
		500 nm		Pentium Pro (150 MHz)
		350 nm		Pentium Pro (166–200 MHz)
		350 nm		Klamath
		250 nm		Deschutes
		250 nm		Katmai		NetBurst
		180 nm		Coppermine		Willamette
		130 nm		Tualatin		Northwood
		130 nm		Banias		Northwood		NetBurst(HT)		NetBurst(×2)
		90 nm		Dothan		Prescott	⇨	Prescott‑2M	⇨	Smithfield
		90 nm		Dothan		~~Tejas~~	→	⇩	→	~~Cedarmill (Tejas)~~
		65 nm		Yonah		~~Nehalem (NetBurst)~~		Cedar Mill	⇨	Presler
		65 nm	Core	Merom	(x86-64) DDR2 + DDR3, 4 cores on mainstream desktop
Bonnell	Bonnell	45 nm	Core	Penryn
	Bonnell	45 nm	Nehalem	Nehalem	HT reintroduced, integrated MC, PCH, L3-cache introduced, 256KiB L2-cache/core, DDR3
	Saltwell	32 nm	Nehalem	Westmere	GPU on same package in 45nm, AES-NI introduced
	Saltwell	32 nm	Sandy Bridge	Sandy Bridge	on-die ring bus, GPU on die, no more non-UEFI motherboards, DDR3
Silvermont	Silvermont	22 nm	Sandy Bridge	Ivy Bridge
	Silvermont	22 nm	Haswell	Haswell	FIVR, DDR3 + DDR3L
	Airmont	14 nm	Haswell	Broadwell
	Airmont		Skylake	Skylake	DDR3L + DDR4
Goldmont	Goldmont			Kaby Lake
				Coffee Lake	DDR4, 6 cores on mainstream desktop
				Amber Lake
	Goldmont Plus			Whiskey Lake
				Coffee Lake Refresh	8 cores on mainstream desktop
				Comet Lake	10 cores on mainstream desktop
				Rocket Lake
Tremont	Tremont	10 nm		Cannon Lake				Hybrid
	Tremont		Sunny Cove	Ice Lake	512KiB L2-cache/core			Lakefield
	Gracemont		Willow Cove	Tiger Lake	X^e graphics engine
	Gracemont		Golden Cove	?