AMD Accelerated Processing Unit
|Models||Desktop E2 Series|
|Cores||2 to 4|
|Fabrication process and transistors||1,178M 32 nm (Llano)
AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices in January 2011. The second-generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third-generation Kaveri for high performance devices was launched in January 2014, while Kabini and Temash for low-power devices were announced in summer 2013.
- 1 History
- 2 Features
- 3 APU-branded platforms
- 3.1 K10 architecture (2011): Llano
- 3.2 Bobcat architecture (2011): Ontario, Zacate, Desna, Hondo
- 3.3 Piledriver architecture (2012): Trinity and Richland
- 3.4 Jaguar architecture (2013): Kabini and Temash
- 3.5 ARM server architecture (2014): Seattle
- 3.6 Steamroller architecture (2014): Kaveri
- 3.7 Puma architecture (2014): Beema and Mullins
- 3.8 Excavator architecture (2015): Carrizo (laptop and mobile processors)
- 3.9 Steamroller architecture (Summer (March-June) 2015): Godavari (desktop Kaveri refresh)
- 3.10 Excavator architecture (2016) Bristol Ridge (desktop Carrizo)
- 4 See also
- 5 References
- 6 External links
The AMD Fusion project started in 2006 with the aim of developing a system on a chip that combined a CPU with a GPU on a single die. AMD took a key step toward realising such a vision when it acquired the graphics chipset manufacturer ATI in 2006. The project reportedly required three internal iterations of the Fusion concept to create a product deemed worthy of release. Reasons contributing to the delay of the project include the technical difficulties of combining a CPU and GPU on the same die at a 45 nm process, and conflicting views on what the role of the CPU and GPU should be within the project.
The first generation desktop and laptop APU, codenamed Llano, was announced on January 4, 2011 at the 2011 CES show in Las Vegas and released shortly after. It featured K10 CPU cores and a Radeon HD 6000-series GPU on the same die on the FM1 socket. An APU for low-power devices was announced as the Brazos platform, based on the Bobcat microarchitecture and a Radeon HD 6000-series GPU on the same die.
At a conference in January 2012, corporate fellow Phil Rogers announced that AMD would re-brand the Fusion platform as the Heterogeneous Systems Architecture (HSA), stating that "it's only fitting that the name of this evolving architecture and platform be representative of the entire, technical community that is leading the way in this very important area of technology and programming development." However, it was later revealed that AMD had been the subject of a trademark infringement lawsuit by the Swiss company Arctic, who used the name "Fusion" for a line of power supplies.
The second generation desktop and laptop APU, codenamed Trinity was announced at AMD's Financial Analyst Day 2010 and released in October 2012. It featured Piledriver CPU cores and Radeon HD 7000 Series GPU cores on the FM2 socket. AMD released a new APU based on the Piledriver microarchitecture on March 12, 2013 for Laptops/Mobile and on June 4, 2013 for desktops under the codename Richland. The second generation APU for low-power devices, Brazos 2.0, used exactly the same APU chip, but ran at higher clock speed and rebranded the GPU as Radeon HD7000 series and used a new IO controller chip.
A third generation of the technology was released on 14 January 2014, featuring greater integration between the CPU and GPU. The desktop and laptop variant is codenamed Kaveri, based on Steamroller architecture, while the low-power variants, codenamed Kabini and Temash, are based on Jaguar architecture.
AMD Heterogeneous System Architecture
AMD is a founding member of the HSA Foundation and is consequently actively working on developing the Heterogeneous System Architecture in co-operation with the other members. The following hardware and software implementations are available in AMD's APU-branded products:
|Type||HSA Feature||First Implemented||Notes|
|Optimized Platform||GPU Compute C++ Support||2012
|Support OpenCL C++ directions and Microsoft’s C++ AMP language extension. This eases programming of both CPU and GPU working together to process support parallel workloads.|
|HSA-aware MMU||GPU can access the entire system memory through the translation services and page fault management of the HSA MMU.|
|Shared Power Management||CPU and GPU now share the power budget. Priority goes to the processor most suited to the current tasks.|
|Architectural Integration||Heterogeneous Memory Management: the CPU's MMU and the GPU's IOMMU share the same address space.||2014
|CPU and GPU now access the memory with the same address space. Pointers can now be freely passed between CPU and GPU, hence enabling zero-copy.|
|Fully coherent memory between CPU & GPU||GPU can now access and cache data from coherent memory regions in the system memory, and also reference the data from CPU's cache. Cache coherency is maintained.|
|GPU uses pageable system memory via CPU pointers||GPU can take advantage of the shared virtual memory between CPU and GPU, and pageable system memory can now be referenced directly by the GPU, instead of being copied or pinned before accessing.|
|System Integration||GPU compute context switch||2015
|Compute tasks on GPU can be context switched, allowing a multi-tasking environment and also faster interpretation between applications, compute and graphics.|
|GPU graphics pre-emption||Long-running graphics tasks can be pre-empted so processes have low latency access to the GPU.|
|Quality of Service||In addition to context switch and pre-emption, hardware resources can be either equalized or prioritized among multiple users and applications.|
|Llano||Trinity||Richland||Kabini & Temash
|Kaveri||Beema & Mullins
|Released||Jan 2011||Aug 2011||Oct 2012||2013||May 2013||Jan 2014||Q2 2014||2015||May 2015|
|Fab (nm)||TSMC 40 nm||GlobalFoundries 32 nm SOI||28||28||28||28||28|
|CPU cores||Bobcat||AMD 10h||Piledriver||Jaguar||Steamroller||Puma||Excavator||Puma+|
|TeraScale 2 (VLIW5)||TeraScale 3 (VLIW4)||Graphics Core Next (Mantle, HSA)|
|Unified Video Decoder||UVD 3||UVD 4||UVD 4.2||TBA||TBA|
|Video Codec Engine||N/A||VCE 1.0||VCE 2.0||TBA||TBA|
|Max. № of displays2||2||2–3||2–4||2||2–4||2||TBA||TBA|
|Direct Rendering Manager/
Mesa 3D driver
- 1 Unified shaders : Texture mapping units : Render output units
- 2 To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed
AMD APUs have a unique architecture: they have AMD CPU modules, cache, and a discrete-class graphics processor all on the same die, using the same bus. This architecture allows for the use of graphics accelerators, such as OpenCL, with the integrated graphics processor. The goal is to create a "fully integrated" APU, which, according to AMD will eventually feature 'heterogeneous cores' capable of processing both CPU and GPU work automatically, depending on the workload requirement.
K10 architecture (2011): Llano
- "Stars" AMD K10-cores
- Integrated Evergreen/VLIW5-based GPU (branded Radeon HD 6000 Series)
- DDR3 memory controller to arbitrate between coherent and non-coherent memory requests. The physical memory is partitioned between the GPU (up to 512 MB) and the CPU (the remainder).
- Unified Video Decoder
- AMD Eyefinity multi-monitor-support
The first generation APU, released in June 2011, was used in both desktops and laptops. It was based on the K10 architecture and built on a 32 nm process featuring two to four CPU cores on a TDP of 65-100 W, and integrated graphics based on the Radeon HD6000 Series with support for DirectX 11, OpenGL 4.2 and OpenCL 1.2. In performance comparisons against the similarly priced Intel Core i3-2105, the Llano APU was criticised for its poor CPU performance and praised for its better GPU performance. AMD was later criticised for abandoning Socket FM1 after one generation.
Bobcat architecture (2011): Ontario, Zacate, Desna, Hondo
- Bobcat-based CPU
- Evergreen/VLIW5-based GPU(branded Radeon HD 6000 Series and Radeon HD 7000 Series)
- PCIe support.
- DDR3 SDRAM memory controller to arbitrate between coherent and non-coherent memory requests. The physical memory is partitioned between the GPU (up to 512 MB) and the CPU (the remainder).
- Unified Video Decoder (UVD)
The AMD Brazos platform was introduced on January 4, 2011 targeting the subnotebook, netbook and low power small form factor markets. It features the 9-watt AMD C-Series APU (codename: Ontario) for netbooks and low power devices as well as the 18-watt AMD E-Series APU (codename: Zacate) for mainstream and value notebooks, all-in-ones and small form factor desktops. Both APUs feature one or two Bobcat x86 cores and a Radeon Evergreen Series GPU with full DirectX11, DirectCompute and OpenCL support including UVD3 video acceleration for HD video including 1080p.
AMD expanded the Brazos platform on June 5, 2011 with the announcement of the 5.9-watt AMD Z-Series APU (codename: Desna) designed for the Tablet market. The Desna APU is based on the 9-watt Ontario APU, energy savings were achieved by lowering the CPU, GPU and north bridge voltages, reducing the idle clocks of the CPU and GPU as well as introducing a hardware thermal control mode. A bidirectional turbo core mode was also introduced.
AMD announced the Brazos-T platform on October 9, 2012. It comprises the 4.5-watt AMD Z-Series APU (codename: Hondo) and the A55T Fusion Controller Hub (FCH), designed for the tablet computer market. The Hondo APU is a redesign of the Desna APU. AMD lowered energy use by optimizing the APU and FCH for tablet computers.
The Deccan platform including Krishna and Wichita APUs were cancelled in 2011. AMD originally planned to release them in the second half 2012.
Piledriver architecture (2012): Trinity and Richland
- Piledriver-based CPU
- Northern Islands/VLIW4-based GPU (branded Radeon HD 7000 and 8000 Series)
- Unified Northbridge includes AMD Turbo Core 3.0, which enables automatic bi-directional power management between CPU modules and GPU. Power to the CPU and GPU is controlled automatically by changing the clock rate depending on the load. For example, for a non-overclocked A10-5800K APU the CPU frequency can change from 1.4 GHz to 4.2 GHz, and the GPU frequency can change from 304 MHz to 800 MHz. In addition, CC6 mode is capable of powering down individual CPU cores, while PC6 mode is able to lower the power on the entire rail."
- AMD HD Media Accelerator - includes AMD Perfect Picture HD, AMD Quick Stream technology, and AMD Steady Video technology.
- Display controllers: AMD Eyefinity-support for multi-monitor set-ups, HDMI, DisplayPort 1.2, DVI
Trinity The first iteration of the second generation platform, released in October 2012, brought improvements to CPU and GPU performance to both desktops and laptops. The platform features 2 to 4 Piledriver CPU cores built on a 32 nm process with a TDP between 65 W and 100 W, and a GPU based on the Radeon HD7000 Series with support for DirectX 11, OpenGL 4.2, and OpenCL 1.2. The Trinity APU was praised for the improvements to CPU performance compared to the Llano APU.
- "Enhanced Piledriver" CPU cores
- Temperature Smart Turbo Core technology. An advancement of the existing Turbo Core technology, which allows internal software to adjust the CPU and GPU clock speed to maximise performance within the constrains of the Thermal design power of the APU.
- New low-power consumption CPUs with only 45 W TDP
Jaguar architecture (2013): Kabini and Temash
- Jaguar (microarchitecture)-based CPU
- Graphics Core Next-based GPU (branded "AMD Radeon R3 graphics"), supports the Mantle API
- Socket FT3 and Socket AM1 support
In January 2013 the Jaguar-based Kabini and Temash APUs were unveiled as the successors of the Bobcat-based Ontario, Zacate and Hondo APUs. The Kabini APU is aimed at the low-power, subnotebook, netbook, ultra-thin and small form factor markets, the Temash APU is aimed at the tablet, ultra-low power and small form factor markets. The two to four Jaguar cores of the Kabini and Temash APUs feature numerous architectural improvements regarding power requirement and performance, such as support for newer x86-instructions, a higher IPC count, a CC6 power state mode and clock gating. Kabini and Temash are AMD's first, and also the first ever quad-core x86 based SoCs. The integrated Fusion Controller Hubs (FCH) for Kabini and Temash are codenamed "Yangtze" and "Salton" respectively. The Yangtze FCH features support for two USB 3.0 ports, two SATA 6 Gbit/s ports, as well as the xHCI 1.0 and SD/SDIO 3.0 protocols for SD-card support. Both chips feature DirectX 11.1-compliant GCN-based graphics as well as numerous Heterogeneous System Architecture (HSA) improvements. They were fabricated at a 28 nm process in an FT3 BGA package by TSMC, and were released on May 23, 2013.
ARM server architecture (2014): Seattle
A Cortex-A57-based 64-bit server solution SoC will be launched in the second half of 2014 and codenamed "Seattle". The first AMD ARM chip has no GPU and is then not an APU, but later will be. Seattle will feature 8 or 16 core variants, with an expected clockspeed over 2 GHz, and will reportedly deliver up to four times the performance of current Opteron X processors. These ARM processors will incorporate SeaMicro freedom fabric on die, offering up to 10 Gbit/s bandwidth, for server usage; additionally, each ARM processor will support up to 64 GB DRAM.
Steamroller architecture (2014): Kaveri
- Steamroller (microarchitecture)-based CPU with 2 to 4 cores
- Graphics Core Next-based GPU with 192–512 shader processors (branded "Radeon R4/5/6/7 graphics")
- 15-95 W TDP
- Fastest laptop processor of this series: 35 W AMD FX-7600P laptop processor
- Fastest desktop processor of this series: 95 W AMD A10-7850K desktop processor (Radeon R7 GCN "Sea Islands"), 3.7 GHz Boost4.0 GHz
- Desktop processor uses Socket FM2+
- Heterogeneous System Architecture-enabled zero-copy through pointer passing
The third generation of the platform, codenamed Kaveri, was partly released on January 14, 2014. Kaveri contains up to four Steamroller CPU cores clocked to 3.7 GHz with a turbo mode of 4 GHz, up to a 512-core Graphics Core Next GPU, two decode units per module instead of one (which allows each core to decode four instructions per cycle instead of two), AMD TrueAudio, Mantle API, an on-chip ARM Cortex-A5 MPCore, and will release with a new socket, FM2+. Ian Cutress and Rahul Garg of Anandtech asserted that Kaveri represented the unified system-on-a-chip realisation of AMD's acquisition of ATI. The performance of the 45W A8-7600 Kaveri APU was found to be similar to that of the 100W Richland part, leading to the claim that AMD made significant improvements in on-die graphics performance per watt; however, CPU performance was found to lag behind similarly-specified Intel processors, a lag that was unlikely to be resolved in the Bulldozer family APUs. The A8-7600 component was delayed from a Q1 launch to an H1 launch because the Steamroller architecture components are alleged to not scale well at higher clock speeds.
AMD announced the release of the Kaveri APU for the mobile market on June 4, 2014 at Computex 2014, shortly after the accidental announcement on the AMD website on May 26, 2014. The announcement included components targeted at the standard voltage, low-voltage, and ultra-low voltage segments of the market. In early-access performance testing of a Kaveri prototype laptop, AnandTech found that the 35W FX-7600P was competitive with the similarly-priced 17W Intel i7-4500U in synthetic CPU-focused benchmarks, and was significantly better than previous integrated GPU systems on GPU-focused benchmarks. Tom's Hardware reported the performance of the Kaveri FX-7600P against the 35W Intel i7-4702MQ, finding that the i7-4702MQ was significantly better than the FX-7600P in synthetic CPU-focused benchmarks, whereas the FX-7600P was significantly better than the i7-4702MQ's Intel HD 4600 iGPU in the four games that could be tested in the time available to the team.
Puma architecture (2014): Beema and Mullins
- Puma (microarchitecture)-based CPU
- Graphics Core Next-based GPU with 128 shader processors (branded "AMD Radeon R4 graphics", (800 MHz over the 600 MHz of "R3" graphics), supports the Mantle API
- Socket FT3 support
Excavator architecture (2015): Carrizo (laptop and mobile processors)
- Excavator (microarchitecture)-based CPU with 4 cores
- Memory controller supports DDR3 SDRAM and DDR4 SDRAM
- 65 W TDP
- Integrates Southbridge
- Announced by AMD on YouTube (Nov 19 2014) -- Preview AMD's next gen APU (Carrizo) with John Byrne (Excavator x86 Core + new Graphics Architecture)
Steamroller architecture (Summer (March-June) 2015): Godavari (desktop Kaveri refresh)
- Steamroller (microarchitecture)-based CPU with 4 cores
- Fastest component: A10-8850K (unlocked) 3.7GHz, Boost4.1GHz, 4MB L2, 856MHz Radeon R7 GCN "Sea Islands" GPU with DirectX 11.2 support
- Memory controller supports DDR3 SDRAM at 2133 MHz
- Socket FM2+
- 95 W TDP
Excavator architecture (2016) Bristol Ridge (desktop Carrizo)
- Excavator (microarchitecture)-based CPU with 4 cores and Radeon graphics
- Memory controller supports DDR4 SDRAM
- 95 W TDP
- AMD Bulldozer
- AMD mobile platform
- List of AMD Accelerated Processing Unit microprocessors
- List of AMD mobile microprocessors
- Unified Video Decoder
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|Wikimedia Commons has media related to AMD Fusion.|
- AMD Fusion Family official website
- HSA Heterogeneous System Architecture Overview on YouTube by Vinod Tipparaju at SC13 in November 2013
- HSA and the software ecosystem