AMD Fusion

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AMD Fusion is the codename for a future next-generation microprocessor design and the product of the merger between AMD and ATI, combining general processor execution as well as 3D geometry processing and other functions of modern GPUs into a single package. AMD's merger with ATI closed on October 25, 2006. This technology is expected to debut in the second half of 2011,[1] as a successor of the latest microarchitecture.

Regarding future AMD microarchitectures beyond the introduction of the latest microarchitecture at mid-2007 and a refresh of the microarchitecture in late 2007 and early 2008; AMD executive VP Henri Richard's June 2006 interview with DigiTimes hints at the future processor development beyond that of the well documented one:

“ Q: What is your broad perspective on the development of AMD processor technology over the next three to four years?

A: Well, as Dirk Meyer commented at our analysts meeting, we're not standing still. We've talked about the refresh of the current K8 architecture that will come in '07, with significant improvements in many different areas of the processor, including integer performance, floating point performance, memory bandwidth, interconnections and so on. You know that platform still has a lot of legs under it, but of course we're not standing still, and there's a next-generation core that's being worked on. I can't give you more details right now, but I think that what's important is that we're establishing clearly that this is a two-horse race. And as you would expect in a race, sometimes, when one horse is a little bit in front of the other, it reverses the situation. But what's important is that it is a race.

 ”
 
— AMD Executive VP, Henri Richard, Source: DigiTimes Interview with Henri Richard.[2]

Contents

[edit] Motivation

In an interview with Exec VP of AMD, Mario Rivas, CRN.com claims that: "'With its Fusion program, AMD hopes to deliver multicore products using different kinds of processing blocks. A GPU, for example, will excel in multiple parallel computational tasks, while the CPU will take on heavy number-crunching duties. The Fusion-based processors, with the CPU and GPU integrated in a single architecture, should make the life of software programmers and application developers much easier,' Rivas added." [3]

[edit] Preliminary information

 This article may require cleanup to meet Wikipedia's quality standards. Please improve this article if you can. (January 2007)
  • A heterogeneous multicore microprocessor architecture, combining a general purpose processing core(s) and basic graphics core(s) into one processor package, with different clocks for the graphics core and the central processing core [4]
  • Four platforms focus on the four different aspects of usage[5]
    • General Purpose
    • Data Centric
    • Graphics Centric
    • Media Centric
  • The Fusion series processor will see new modular design methodology named "M-SPACE", such that design of future multi-core processors will have a wider range of combinations, as well as gaining enhanced flexibility, thus to minimize the architectural changes for different combinations of components. Benefitted from this initiative by AMD, graphics core can be changed without much re-design of the whole core [6]
  • Fusion products will include at least 16 PCI Express (presumably version 3.0) lanes
  • The implementation of UVD in silicon [7] for full hardware decoding of MPEG2, VC-1 and H.264 video streams on supported software
  • The first Z-RAM design on a 45 nm fabrication process node was completed in 2006 [8], together with the renewal of Z-RAM license. This coincides with the process node that Fusion processors are expected to be fabricated around the timeframe. This also coincides with the AMD official roadmap for larger L3 caches after 2009. Thus it was rumoured that AMD will likely to feature Z-RAM for larger L3 cache in Fusion products.
  • A new set of instructions and development libraries for Fusion were being developed [9], and was revealed to be a new iteration of SSE, named XOP, FMA4 and CVT16 announced in August 2007[10] and revised in May 2009[11].
  • According to Dave Orton, Fusion will have 10% more pins than a "normal CPU" [12] but he failed to further elaborate on what is a "normal CPU".
  • Employ Socket FS1 [13], and two other sockets so that each targeted at different products, Socket FS1 is for mobile parts, another for desktop products and the other server processors.

[edit] Implementations

Two implementations were announced publicly during AMD events.

[edit] Falcon

  • Codenamed the Falcon family
  • Announced in AMD Technology Analyst Day July 2007
  • Incorporation with GPU cores
  • Target market:
    • Originally planned with the codenamed Bulldozer processor cores focusing on desktop market with TDP of 10 to 100 Watts
    • An option to be implemented into mobile phones, UMPC and small multimedia devices [14], with the codenamed Bobcat processor core focusing on low power consumption (1 to 10 Watts TDP) computations for handheld devices such as UMPC

[edit] Swift

  • The plan was later changed to bring the first product of Fusion (codenamed Swift [15])
  • Announced in AMD Financial Analyst Day December 2007
  • Based on the codenamed Stars CPU cores (K10 architecture) made on 45 nm process instead of Bulldozer and Bobcat cores
  • Aimed at notebook market
  • Native CPU die with a GPU core on the same package [16], implementing Socket FS1, with two variants [13]:
    • White Swift: Single CPU core [16]
    • Black Swift: Dual CPU core [16]
  • Support for DDR3 [16]
  • Incorporation of full DirectX-compliant GPU core(s): RV710-level, codenamed Kong [17]
  • Codenamed Onion, new interconnect [17]
  • Codenamed Garlic, new memory interface for reduced memory reading latencies of the GPU [17]

[edit] Media discussions

[edit] Anticipated competitors

  • Nehalem, Intel's one to eight core processor microarchitecture possibly including an integrated graphics core [18].
  • VIA CoreFusion, a VIA product focused on low-power consumption computing market.

[edit] See also

[edit] References

  1. ^ Hruska, Joel (November 14, 2008). "AMD Fusion now pushed back to 2011". Ars Technica. http://arstechnica.com/news.ars/post/20081114-amd-fusion-now-pushed-back-to-2011.html. 
  2. ^ http://www.digitimes.com/news/a20060628VL201.html
  3. ^ "AMD sees Vista driving demand for graphics horsepower". crn.com. 2006-12-14. http://www.crn.com.au/story.aspx?CIID=70189&src=site-marq. 
  4. ^ Fudzilla report
  5. ^ AMD ATI merger - Official Investor PresentationPDF (846 KiB), retrieved July 24, 2006
  6. ^ Fudzilla report
  7. ^ The Inquirer report, retrieved September 12, 2007
  8. ^ ISi announcementPDF (77.4 KiB), retrieved August 14, 2007
  9. ^ Fudzilla report
  10. ^ http://developer.amd.com/sse5.jsp
  11. ^ "AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions". AMD. May 1, 2009. http://support.amd.com/us/Processor_TechDocs/43479.pdf. 
  12. ^ Fudzilla report
  13. ^ a b AMD Financial Analyst Day 2007 presentation, presented by Mario Rivas, page 22 of 28. Retrieved December 14, 2007
  14. ^ Fudzilla report
  15. ^ AMD Financial Analyst Day 2007 presentation, presented by Mario Rivas, page 16 of 28. Retrieved December 14, 2007
  16. ^ a b c d e (Chinese) HKEPC report, retrieved March 4, 2008
  17. ^ a b c d (Chinese) HKEPC report, retrieved August 20, 2008
  18. ^ The Inquirer report, retrieved September 18, 2007

[edit] External links

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