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* [[Skylake (microarchitecture)|Skylake]]: new 14 nm microarchitecture, released August 5, 2015.
* [[Skylake (microarchitecture)|Skylake]]: new 14 nm microarchitecture, released August 5, 2015.
** [[Goldmont]]: 14&nbsp;nm [[Atom (system on chip)|Atom]] microarchitecture, borrows heavily from Skylake processors, released April 2016.<ref name="software.intel.com">{{cite web |title=Intel Software Development Emulator |url=http://software.intel.com/en-us/articles/intel-software-development-emulator}}</ref><ref name="forums.anandtech.com">{{cite web |title="Goldmont"- the sequel to Silvermont Atom? |url=http://forums.anandtech.com/showthread.php?t=2332517}}</ref>
** [[Goldmont]]: 14&nbsp;nm [[Atom (system on chip)|Atom]] microarchitecture, borrows heavily from Skylake processors, released April 2016.<ref name="software.intel.com">{{cite web |title=Intel Software Development Emulator |url=http://software.intel.com/en-us/articles/intel-software-development-emulator}}</ref><ref name="forums.anandtech.com">{{cite web |title="Goldmont"- the sequel to Silvermont Atom? |url=http://forums.anandtech.com/showthread.php?t=2332517}}</ref>
** [[Kaby Lake]]: released October 2016 (socketed desktop models to be released in 2017), successor to Skylake, broke Intel's [[Tick-Tock model|Tick-Tock schedule]] due to delays with the 10&nbsp;nm process.
** [[Kaby Lake]]: expected in early 2017, successor to Skylake, broke Intel's [[Tick-Tock model|Tick-Tock schedule]] due to delays with the 10&nbsp;nm process.
** [[Cannonlake]]: expected in late 2017. It will be a 10&nbsp;nm shrink of Kaby Lake. Formerly called Skymont.
** [[Cannonlake]]: expected in late 2017. It will be a 10&nbsp;nm shrink of Kaby Lake. Formerly called Skymont.
** [[Coffee Lake]]: expected in early 2018. It will be a 14&nbsp;nm successor of Kaby Lake.
* [[Ice Lake]]: new 10&nbsp;nm microarchitecture, expected in 2018.
* [[Ice Lake]]: new 10&nbsp;nm microarchitecture, expected in late 2018.
** [[Tiger Lake (microarchitecture)|Tiger Lake]]: an update of Ice Lake, serving as "semi-Tock" of the Intel's Tick-Tock strategy, expected in 2019.
** [[Tiger Lake (microarchitecture)|Tiger Lake]]: an update of Ice Lake, serving as "semi-Tock" of the Intel's Tick-Tock strategy, expected in 2019.


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==Roadmap==
==Roadmap==
{| class="wikitable" style="margin:0.5em auto; text-align:left"
{{:Tick-Tock model/main roadmap}}
|-
! rowspan="2" | Archi&shy;tectural change
! rowspan="2" | [[Semiconductor device fabrication|Fabri&shy;cation process]]
! rowspan="2" | Micro&shy;archi&shy;tecture
! rowspan="2" | Code&shy;names
! rowspan="2" | Release date
! colspan="5" | Processors
|-
! 8P/4P Server
! 4P/2P Server/<abbr title="Workstation">WS</abbr>
! Enthusiast/&#8203;<abbr title="Workstation">WS</abbr>
! Desktop
! Mobile
|-
| [[Tick-Tock model|Tick]] (new fabri&shy;cation process)
| rowspan="2" | [[65 nanometer|65 nm]]
| [[P6 (microarchitecture)|P6]], [[NetBurst (microarchitecture)|NetBurst]]
| [[Pentium D#Presler|Presler]], [[Pentium 4#Cedar Mill|Cedar Mill]], [[Yonah (microprocessor)|Yonah]]
| 2006-01-05
|
|
| [[Pentium D#Presler|Presler]]
| [[Pentium 4#Cedar Mill|Cedar Mill]]
| [[Yonah (microprocessor)|Yonah]]
|-
| [[Tick-Tock model|Tock]] (new micro&shy;archi&shy;tecture)
| rowspan="2" | [[Core (microarchitecture)|Core]]
| Merom<ref>{{cite web|last=Crothers |first=Brooke |url=http://news.cnet.com/8301-13924_3-10160673-64.html |title=Intel moves up rollout of new chips &#124; Nanotech - The Circuits Blog - CNET News |publisher=News.cnet.com |date=2009-02-10 |accessdate=2014-02-25}}</ref>
| 2006-07-27<ref>[http://www.intel.com/pressroom/archive/releases/20060105corp.htm Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing], [http://www.intel.com/pressroom/archive/releases/20060727comp.htm Intel Unveils World's Best Processor]</ref>
| [[Tigerton (microprocessor)|Tigerton]]
| [[Woodcrest (microprocessor)|Woodcrest]]<br/>[[Clovertown (microprocessor)|Clovertown]]
| [[Kentsfield (microprocessor)|Kentsfield]]
| [[Conroe (microprocessor)|Conroe]]
| [[Merom (microprocessor)|Merom]]
|-
| Tick
| rowspan="2" | [[45 nanometer|45 nm]]
| [[Penryn (microarchitecture)|Penryn]]
| 2007-11-11<ref>[http://www.intel.com/pressroom/archive/releases/20080107comp.htm Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology]</ref>
| [[Dunnington (microprocessor)|Dunnington]]
| [[Harpertown (microprocessor)|Harpertown]]
| [[Yorkfield]]
| [[Wolfdale (microprocessor)|Wolfdale]]
| [[Penryn (microprocessor)|Penryn]]
|-
| Tock
| rowspan="2" | [[Nehalem (microarchitecture)|Nehalem]]
| [[Nehalem (microarchitecture)|Nehalem]]
| 2008-11-17<ref>[http://www.intel.com/pressroom/archive/releases/2008/20081117comp_sm.htm Intel Launches Fastest Processor on the Planet]</ref>
| [[List of Intel Xeon microprocessors#"Beckton" (45 nm)|Beckton]]
| [[List of Intel Xeon microprocessors#"Gainestown" (45 nm)|Gainestown]]
| [[Bloomfield (microprocessor)|Bloomfield]]
| [[Lynnfield (microprocessor)|Lynnfield]]
| [[Clarksfield (microprocessor)|Clarksfield]]
|-
| Tick
| rowspan="2" | [[32 nanometer|32 nm]]
| [[Westmere (microarchitecture)|Westmere]]
| 2010-01-04<ref name="MarkBohr">http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf</ref><ref>[http://www.intel.com/technology/architecture-silicon/32nm/index.htm Revolutionizing How We Use Technology—Today and Beyond]</ref>
| [[Westmere-EX]]
| [[Gulftown|Westmere-EP]]
| [[Gulftown]]
| [[Clarkdale (microprocessor)|Clarkdale]]
| [[Arrandale]]
|-
| Tock
| rowspan="2" | [[Sandy Bridge]]
| [[Sandy Bridge]]
| 2011-01-09<ref>[http://news.cnet.com/8301-13924_3-20022893-64.html Intel Sandy Bridge chip coming January 5]</ref>
| (Skipped)<ref>[http://news.softpedia.com/news/Intel-Ivy-Bridge-CPU-Range-Complete-by-Next-Year-263451.shtml Intel Ivy Bridge CPU Range Complete by Next Year]</ref>
| [[Sandy Bridge|Sandy Bridge-EP]]
| [[Sandy Bridge-E]]
| [[Sandy Bridge]]
| [[Sandy Bridge|Sandy Bridge-M]]
|-
| Tick
| rowspan="3" | [[22 nanometer|22 nm]]<ref name="22nm" />
| [[Ivy Bridge (microarchitecture)|Ivy Bridge]]
| 2012-04-29
| Ivy Bridge-EX<ref name="vr-z">http://vr-zone.com/articles/ivy-bridge-ep-and-ex-coming-up-in-a-year-s-time--the-multi-socket-platform-heaven/15488.html</ref>
| Ivy Bridge-EP<ref name="vr-z" />
| Ivy Bridge-E<ref>[http://www.techspot.com/news/47849-ivy-bridge-e-delayed-until-second-half-of-2013.html Ivy Bridge-E Delayed Until Second Half of 2013]</ref>
| [[Ivy Bridge (microarchitecture)|Ivy Bridge]]
| [[Ivy Bridge (microarchitecture)|Ivy Bridge-M]]
|-
| Tock
| rowspan="3" | [[Haswell (microarchitecture)|Haswell]]
| [[Haswell (microarchitecture)|Haswell]]
| 2013-06-02
| Haswell-EX
| Haswell-EP
| Haswell-E
| Haswell-DT<ref name="hsw-specs">{{cite web|url=http://technewspedia.com/leaked-specifications-of-haswell-gt1gt2gt3-igp |title=Leaked specifications of Haswell GT1/GT2/GT3 IGP |publisher=Tech News Pedia |date=2012-05-20 |accessdate=2014-02-25}}</ref>
|
* Haswell-MB (notebooks)
* Haswell-LP (ultrabooks)<ref name="hsw-specs" />
|-
| rowspan="1" | Refresh
| rowspan="1" | [[Haswell Refresh]], [[Devil's Canyon (CPU)|Devil's Canyon]]<ref name="golem">{{cite web| url = http://www.golem.de/news/intel-core-i7-4790k-devils-canyon-mit-bis-zu-4-4-ghz-aber-ohne-verloeteten-deckel-1406-106846.html | date = Jun 3, 2014 | title = Devils Canyon mit bis zu 4,4 GHz, ohne verlöteten Deckel | publisher = golem.de}}</ref>
| rowspan="1" | 2014-06
| rowspan="1" |
| rowspan="1" |
| rowspan="1" |
| rowspan="1" |
| rowspan="1" |
|-
| Tick
| rowspan="4" | [[14 nanometer|14 nm]]<ref name="22nm">[http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf 22nm technology. May 2011]</ref>
| [[Broadwell (microarchitecture)|Broadwell]]<ref name="BroadwellSA">[http://semiaccurate.com/2011/03/31/after-intels-haswell-comes-broadwell-sk/ After Intel's Haswell comes Broadwell - SemiAccurate]</ref>
| 2014-09-05
| Broadwell-EX <ref name="BroadwellEP">[http://www.kitguru.net/components/cpu/anton-shilov/intel-to-release-22-core-xeon-e5-v4-broadwell-ep-late-in-2015-company/ Intel to release 22-core Xeon E5 v4 “Broadwell-EP” late in 2015]</ref>
| Broadwell-EP <ref name="BroadwellEP" />
| [[Broadwell (microarchitecture)#.22Broadwell-E.22_.2814_nm.29|Broadwell-E]]
|
|
|-
| Tock
| rowspan="4" | [[Skylake (microarchitecture)|Skylake]]<ref name="BroadwellSA" />
| [[Skylake (microarchitecture)|Skylake]]<ref name="BroadwellSA" />
| 2015-08-05<ref>[http://www.digitaltrends.com/computing/unlocked-intel-skylake-s-processors-reportedly-coming-august-5th/ The wait for Skylake is almost over, first desktop chips likely to hit August 5]</ref>
| Skylake-EX
| Skylake-EP
|
|
|
|-
| rowspan="2" | Optimizations (refreshes)<ref name="anandtech-pao">{{cite web|title=Intel’s ‘Tick-Tock’ Seemingly Dead, Becomes ‘Process-Architecture-Optimization’|url=http://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization|website=Anandtech|accessdate=23 March 2016}}</ref><ref name="wccftech">{{cite web| url = http://wccftech.com/intel-14nm-kaby-lake-haswell-refresh-platform-detailed-launching-2h-2016-256-mb-edram-hseries-91w-kseries-unveiled/ | date = July 2015 | title = Intel 14nm Kaby Lake “Skylake Refresh” Platform Detailed – Launching in 2H 2016, 256 MB eDRAM H-Series and 91W K-Series Unveiled | publisher = wccftech.com | quote = The Kaby Lake platform will be similar to Skylake platform that launches this year and will act as a platform refresher}}</ref><ref name="legitreviews">{{cite web| url = http://www.legitreviews.com/intel-releasing-14nm-kaby-lake-processor-in-2016-ahead-of-10nm-cannonlake_168841/ | date = 2015-07-08 | title = Intel Releasing 14nm Kaby Lake Processor in 2016 Ahead of 10nm Cannonlake | publisher = legitreviews.com | quote = We have long known that Intel was planning a ‘Skylake Refresh’ that has always been on the roadmap between Skylake and Cannonlake, but it appears that refresh might be going by the code name Kaby lake now.}}</ref><ref name="wccftech20160120-Icelake" />
| [[Kaby Lake]]<ref name="arstechnica">{{cite web| url = http://arstechnica.com/gadgets/2015/07/intel-confirms-tick-tock-shattering-kaby-lake-processor-as-moores-law-falters/ | date = Jul 15, 2015 | title = Intel confirms tick-tock shattering Kaby Lake processor as Moore’s Law falters | publisher = ArsTechnica.com | quote = the switch to 10nm manufacturing has been delayed until the second half of 2017.}}</ref>
| Q1 2017
|
|
|
|
|
|-
|[[Coffee Lake]]
|1H 2018<ref>http://wccftech.com/intel-14nm-coffee-lake-10nm-cannonlake-2018/</ref>
|
|
|
|
|
|-
| Process
| rowspan="3" | [[10 nanometer|10 nm]]<ref name="NewRoadmap">{{cite web|url=http://hexus.net/tech/news/cpu/39381-intel-currently-developing-14nm-aiming-towards-5nm-chips/ |title=Intel currently developing 14nm, aiming towards 5nm chips - CPU - News |publisher=HEXUS.net |date=2012-05-15 |accessdate=2014-02-25}}</ref>
| [[Cannonlake]]
|2H 2017<ref name="arstechnica" />
|
|
|
|
|
|-
| Architecture
| rowspan="3" | [[Ice Lake]]<ref name="wccftech20160120-Icelake">{{cite web | url=http://wccftech.com/intel-10nm-cannonlake-ice-lake-tiger-lake-cpu/ | title=Intel’s Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2018 and 10nm Tiger Lake Family in 2019 | work=WCCFTech | date=2016-01-20}}</ref>
| [[Ice Lake]]<ref>http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx</ref>
| 2018
|
|
|
|
|
|-
| Optimization<ref name="wccftech20160120-Icelake" />
| [[Tigerlake]]<ref name="wccftech20160120-Icelake" />
| 2019
|
|
|
|
|
|-
| Process
| rowspan="3" | [[7 nanometer|7 nm]]<ref name="NewRoadmap" />
|
|
|
|
|
|
|
|-
| Architecture
| rowspan="3" |
|
|
|
|
|
|
|
|-
|Optimization
|
|
|
|
|
|
|
|-
| Process
| rowspan="3" | [[5 nanometer|5 nm]]<ref name="NewRoadmap" />
|
|
|
|
|
|
|
|-
| Architecture
| rowspan="2" |
|
|
|
|
|
|
|
|-
|Optimization
|
|
|
|
|
|
|
|}


===Atom===
{{anchor|atom-roadmap}}
{{anchor|atom-roadmap}}
{| class="wikitable collapsible" style="margin:0.5em auto; text-align: center; min-width:40em;"
{{:Tick-Tock model/Atom roadmap}}
! colspan="12" | Atom Roadmap<ref name="atom-ticktock">{{cite web |title=Intel’s Silvermont Architecture Revealed: Getting Serious About Mobile |url=http://www.anandtech.com/show/6936/intels-silvermont-architecture-revealed-getting-serious-about-mobile |website=[[AnandTech]]}}</ref>
|-
! rowspan="2" |
! rowspan="2" | Fabrication process
! rowspan="2" | Microarchitecture
! rowspan="2" | Release date
! colspan="8" | Processors/SoCs
|-
! <abbr title="Mobile Internet device">MID</abbr>, Smartphone
! Tablet
! Netbook
!Nettop
! Embedded
! Server
!Communication
! <abbr title="Consumer Electronics">CE</abbr>
|-
| Tick
| rowspan="2" | [[45 nanometer|45 nm]]
| rowspan="2" | [[Bonnell (microarchitecture)|Bonnell]]
| <!-- April -->2008
| [[Silverthorne (microprocessor)|Silverthorne]]<!-- Menlow -->
| {{n/a}}
| colspan="2" | [[Diamondville (microprocessor)|Diamondville]]
| rowspan="2" | [[Tunnel Creek (microprocessor)|Tunnel Creek]] & Stellarton
| rowspan="2" {{n/a}}
|
| [[Sodaville (SoC)|Sodaville]]
|-
| Tock
| 2010
| colspan="2" | [[Lincroft (microprocessor)|Lincroft]]<!-- Moorestown --><!-- Oak Trail -->
| colspan="2" | [[Pineview (microprocessor)|Pineview]]
|
| [[Groveland (SoC)|Groveland]]
|-
| Tick
| [[32 nanometer|32 nm]]
| Saltwell
| <!-- November -->2011
| Medfield ([[Penwell (SoC)|Penwell]] & Lexington) & Clover Trail+ (Cloverview) <!-- Clover Trail+ smartphones, see for example http://newsroom.intel.com/community/intel_newsroom/blog/2013/02/24/intel-accelerates-mobile-computing-push or http://www.tomshardware.com/reviews/atom-z2580-clover-trail-medfield,3446.html -->
| Clover Trail ([[Cloverview (SoC)|Cloverview]]) <!-- Penwell is used in some tablets, see for example http://www.intel.com/content/www/us/en/education-solutions/tablets.html -->
| colspan="2" | Cedar Trail ([[Cedarview (microprocessor)|Cedarview]])
| {{unk}}
| [[Centerton (SoC)|Centerton]] & Briarwood
| {{unk}}
| [[Berryville (SoC)|Berryville]]
|-
| Tick
| [[22 nanometer|22 nm]]
| [[Silvermont]]
| 2013
| Merrifield (Tangier) <ref>{{cite web |last=Hiroshige |first=Goto |title=Intel Products for Tablets & SmartPhones |work=標準 |publisher=Impress |url=http://pc.watch.impress.co.jp/video/pcw/docs/569/575/p2.pdf}}</ref> & Moorefield (Anniedale)<ref>{{cite web |title=Import Data and Price of anniedale |url=https://www.zauba.com/import-anniedale-hs-code.html}}</ref> & Slayton
| Bay Trail-T (Valleyview)
| Bay Trail-M (Valleyview)
| Bay Trail-D (Valleyview)
| Bay Trail-I (Valleyview)
| Avoton
| Rangeley
| {{unk}}
|-
| Tick
| rowspan="2" | [[14 nanometer|14 nm]]<ref name="atom-ticktock" />
| Airmont
| 2014
| Binghamton & Riverton
| Cherry Trail-T (Cherryview) <ref>{{cite web |title=アウトオブオーダーと最新プロセスを採用する今後のAtom |url=http://pc.watch.impress.co.jp/docs/column/ubiq/20121130_576105.html}}</ref>
| colspan="3" | Braswell <ref>{{cite web|title=Products (Formerly Braswell)|url=http://ark.intel.com/products/codename/66094/Braswell#@All|website=Intel® ARK (Product Specs)|accessdate=5 April 2016}}</ref>
| Denverton
| {{unk}}
| {{unk}}
|-
| Tock
| [[Goldmont]]<ref>{{cite news|last1=Smith|first1=Ryan|last2=Cutress|first2=Ian|title=Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled|url=http://www.anandtech.com/show/10288/intel-broxton-sofia-smartphone-socs-cancelled|accessdate=29 June 2016|publisher=Anandtech.com|date=29 April 2016}}</ref>
| 2016
| Broxton {{Cancelled}}
| Broxton {{Cancelled}}<br/>Apollo Lake
| Apollo Lake
| {{unk}}
| {{unk}}
| {{unk}}
| {{unk}}
| {{unk}}
|}

{{Intel processor roadmap}}


== See also ==
== See also ==
Line 140: Line 454:
* [http://ark.intel.com/ Intel Automated Relational Knowledgebase]
* [http://ark.intel.com/ Intel Automated Relational Knowledgebase]


{{Intel processors}}
{{Intel processor roadmap}}
{{Intel processor roadmap}}
{{Intel processors}}


[[Category:Intel microprocessors|*]]
[[Category:Intel microprocessors|*]]

Revision as of 15:55, 1 December 2016

The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick-Tock model.

x86 microarchitectures

Year Microarchitecture Pipeline stages max. Clock
1989 486 (80486) 3 100 MHz
1993 P5 (Pentium) 5 300 MHz
1995 P6 (Pentium II) 14 (17 with load & store/retire) 450 MHz
1999 P6 (Pentium III) 12 (15 with load & store/retire) 450~1400 MHz
2000 NetBurst (Pentium 4) 20 800~3466 MHz
2003 Pentium M 10 (12 with fetch/retire) 400~1000 MHz
2004 Prescott 31 3800 MHz
2006 Intel Core 12 (14 with fetch/retire) 3000 MHz
2008 Nehalem 20 3000 MHz
2008 Bonnell 16 (20 with prediction miss) 2100 MHz
2011 Sandy Bridge 14 (16 with fetch/retire) 4000 MHz
2013 Silvermont 14-17 (16-19 with fetch/retire) 2670 MHz
2013 Haswell 14 (16 with fetch/retire) ≈4000 MHz
2015 Skylake 14 (16 with fetch/retire) ≈4000 MHz
2016 Kaby Lake ? ?
  • pre-P5:
    • 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.
    • 186: included a DMA controller, interrupt controller, timers, and chip select logic.
    • 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086.
    • i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since.
    • i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining.
  • P5: original Pentium microprocessors, first x86 processor with super scaling feature, branch prediction and RISC μop decode scheme.
  • P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, integrated register renaming and Out of Order execution.
  • NetBurst: Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache.
  • Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
  • Intel Core: reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion&enhanced micro-op fusion with wider front end and decoder, larger Out of Order core and renamed register, support loop stream detector and large shadow register file.
    • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, and SSE4.1 instructions, support xop and F/SAVE&F/STORE instruction and enhance register alias table and larger integer register file.
  • Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die.
    • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
  • Bonnell: 45 nm, low-power, in-order microarchitecture for use in Atom processors.
    • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
  • Larrabee (cancelled 2010): multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
  • Sandy Bridge: released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
    • Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.
  • Silvermont: 22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
    • Airmont: 14 nm shrink of the Silvermont microarchitecture.
  • Haswell: 22 nm microarchitecture, released June 3, 2013.
    • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
  • Skylake: new 14 nm microarchitecture, released August 5, 2015.
    • Goldmont: 14 nm Atom microarchitecture, borrows heavily from Skylake processors, released April 2016.[2][3]
    • Kaby Lake: expected in early 2017, successor to Skylake, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
    • Cannonlake: expected in late 2017. It will be a 10 nm shrink of Kaby Lake. Formerly called Skymont.
  • Ice Lake: new 10 nm microarchitecture, expected in 2018.
    • Tiger Lake: an update of Ice Lake, serving as "semi-Tock" of the Intel's Tick-Tock strategy, expected in 2019.

Itanium microarchitectures

Roadmap

Archi­tectural change Fabri­cation process Micro­archi­tecture Code­names Release date Processors
8P/4P Server 4P/2P Server/WS Enthusiast/​WS Desktop Mobile
Tick (new fabri­cation process) 65 nm P6, NetBurst Presler, Cedar Mill, Yonah 2006-01-05 Presler Cedar Mill Yonah
Tock (new micro­archi­tecture) Core Merom[5] 2006-07-27[6] Tigerton Woodcrest
Clovertown 		Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11[7] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 2008-11-17[8] Beckton Gainestown Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 2010-01-04[9][10] Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge 2011-01-09[11] (Skipped)[12] Sandy Bridge-EP Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm[13] Ivy Bridge 2012-04-29 Ivy Bridge-EX[14] Ivy Bridge-EP[14] Ivy Bridge-E[15] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell 2013-06-02 Haswell-EX Haswell-EP Haswell-E Haswell-DT[16]
  • Haswell-MB (notebooks)
  • Haswell-LP (ultrabooks)[16]
Refresh Haswell Refresh, Devil's Canyon[17] 2014-06
Tick 14 nm[13] Broadwell[18] 2014-09-05 Broadwell-EX [19] Broadwell-EP [19] Broadwell-E
Tock Skylake[18] Skylake[18] 2015-08-05[20] Skylake-EX Skylake-EP
Optimizations (refreshes)[21][22][23][24] Kaby Lake[25] Q1 2017
Coffee Lake 1H 2018[26]
Process 10 nm[27] Cannonlake 2H 2017[25]
Architecture Ice Lake[24] Ice Lake[28] 2018
Optimization[24] Tigerlake[24] 2019
Process 7 nm[27]
Architecture
Optimization
Process 5 nm[27]
Architecture
Optimization

Atom Roadmap[29]
Fabrication process Microarchitecture Release date Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server Communication CE
Tick 45 nm Bonnell 2008 Silverthorne — Diamondville Tunnel Creek & Stellarton — Sodaville
Tock 2010 Lincroft Pineview Groveland
Tick 32 nm Saltwell 2011 Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) Clover Trail (Cloverview) Cedar Trail (Cedarview) Un­known Centerton & Briarwood Un­known Berryville
Tick 22 nm Silvermont 2013 Merrifield (Tangier) [30] & Moorefield (Anniedale)[31] & Slayton Bay Trail-T (Valleyview) Bay Trail-M (Valleyview) Bay Trail-D (Valleyview) Bay Trail-I (Valleyview) Avoton Rangeley Un­known
Tick 14 nm[29] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview) [32] Braswell [33] Denverton Un­known Un­known
Tock Goldmont[34] 2016 Broxton Cancelled Broxton Cancelled
Apollo Lake 		Apollo Lake Un­known Un­known Un­known Un­known Un­known

See also

References

  1. ^ "An Update On Our Graphics-related Programs". May 25, 2010.
  2. ^ "Intel Software Development Emulator".
  3. ^ ""Goldmont"- the sequel to Silvermont Atom?".
  4. ^ Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. Retrieved 2007-10-05.
  5. ^ Crothers, Brooke (2009-02-10). "Intel moves up rollout of new chips | Nanotech - The Circuits Blog - CNET News". News.cnet.com. Retrieved 2014-02-25.
  6. ^ Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing, Intel Unveils World's Best Processor
  7. ^ Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology
  8. ^ Intel Launches Fastest Processor on the Planet
  9. ^ http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf
  10. ^ Revolutionizing How We Use Technology—Today and Beyond
  11. ^ Intel Sandy Bridge chip coming January 5
  12. ^ Intel Ivy Bridge CPU Range Complete by Next Year
  13. ^ a b 22nm technology. May 2011
  14. ^ a b http://vr-zone.com/articles/ivy-bridge-ep-and-ex-coming-up-in-a-year-s-time--the-multi-socket-platform-heaven/15488.html
  15. ^ Ivy Bridge-E Delayed Until Second Half of 2013
  16. ^ a b "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. Retrieved 2014-02-25.
  17. ^ "Devils Canyon mit bis zu 4,4 GHz, ohne verlöteten Deckel". golem.de. Jun 3, 2014.
  18. ^ a b c After Intel's Haswell comes Broadwell - SemiAccurate
  19. ^ a b Intel to release 22-core Xeon E5 v4 “Broadwell-EP” late in 2015
  20. ^ The wait for Skylake is almost over, first desktop chips likely to hit August 5
  21. ^ "Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'". Anandtech. Retrieved 23 March 2016.
  22. ^ "Intel 14nm Kaby Lake "Skylake Refresh" Platform Detailed – Launching in 2H 2016, 256 MB eDRAM H-Series and 91W K-Series Unveiled". wccftech.com. July 2015. The Kaby Lake platform will be similar to Skylake platform that launches this year and will act as a platform refresher
  23. ^ "Intel Releasing 14nm Kaby Lake Processor in 2016 Ahead of 10nm Cannonlake". legitreviews.com. 2015-07-08. We have long known that Intel was planning a 'Skylake Refresh' that has always been on the roadmap between Skylake and Cannonlake, but it appears that refresh might be going by the code name Kaby lake now.
  24. ^ a b c d "Intel's Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2018 and 10nm Tiger Lake Family in 2019". WCCFTech. 2016-01-20.
  25. ^ a b "Intel confirms tick-tock shattering Kaby Lake processor as Moore's Law falters". ArsTechnica.com. Jul 15, 2015. the switch to 10nm manufacturing has been delayed until the second half of 2017.
  26. ^ http://wccftech.com/intel-14nm-coffee-lake-10nm-cannonlake-2018/
  27. ^ a b c "Intel currently developing 14nm, aiming towards 5nm chips - CPU - News". HEXUS.net. 2012-05-15. Retrieved 2014-02-25.
  28. ^ http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx
  29. ^ a b "Intel's Silvermont Architecture Revealed: Getting Serious About Mobile". AnandTech.
  30. ^ Hiroshige, Goto. "Intel Products for Tablets & SmartPhones" (PDF). 標準. Impress.
  31. ^ "Import Data and Price of anniedale".
  32. ^ "アウトオブオーダーと最新プロセスを採用する今後のAtom".
  33. ^ "Products (Formerly Braswell)". Intel® ARK (Product Specs). Retrieved 5 April 2016.
  34. ^ Smith, Ryan; Cutress, Ian (29 April 2016). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled". Anandtech.com. Retrieved 29 June 2016.

External links

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