Ice Lake (microprocessor): Difference between revisions
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* L1 instruction/data cache: 32KB/48 KiB; L2 cache: 512 KiB<ref name=":0" /> |
* L1 instruction/data cache: 32KB/48 KiB; L2 cache: 512 KiB<ref name=":0" /> |
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* [[DisplayPort]] 1.4a with Display Stream Compression; HDMI 2.0 |
* [[DisplayPort]] 1.4a with Display Stream Compression; HDMI 2.0 |
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*[[Thunderbolt (interface)|Thunderbolt]] 3 over Type C natively on- |
*[[Thunderbolt (interface)|Thunderbolt]] 3 over Type C natively on-die<ref>https://newsroom.intel.com/news/intel-takes-steps-enable-thunderbolt-3-everywhere-releases-protocol/#gs.19wo3z</ref><ref>https://fuse.wikichip.org/news/2318/ice-lake-brings-a-new-cpu-gpu-ipu-and-i-os-to-follow-by-tiger-lake-next-year/</ref> |
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* Six new [[AVX-512#CPUs_with_AVX-512|AVX-512]] instructions: VPOPCNTDQ, VBMI2, BITALG, VPCLMULQDQ, GFNI, and VAES |
* Six new [[AVX-512#CPUs_with_AVX-512|AVX-512]] instructions: VPOPCNTDQ, VBMI2, BITALG, VPCLMULQDQ, GFNI, and VAES |
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* Integrated support for [[Wi-Fi]] 6 ([[IEEE 802.11ax|802.11ax]]) |
* Integrated support for [[Wi-Fi]] 6 ([[IEEE 802.11ax|802.11ax]]) |
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Revision as of 12:35, 13 May 2019
| Cache | |
|---|---|
| L1 cache | 80 KiB per core (32 instructions + 48 data) |
| L2 cache | 512 KiB per core |
| Architecture and classification | |
| Instructions | x86-64 |
| Extensions | |
| Physical specifications | |
| Transistors |
|
| GPU | Gen11 |
| History | |
| Predecessors | Desktop: Coffee Lake Mobile: Whiskey Lake (3rd Optimization) [1][2] Mobile: Cannon Lake (Process) Server: Cooper Lake (2nd Optimization) |
| Successor | Tiger Lake (Optimization) |
Ice Lake is Intel's codename for the 10th generation Intel Core processors based on the new Sunny Cove microarchitecture. Ice Lake is expected to replace the Coffee Lake, Whiskey Lake, Kaby Lake and Cannon Lake microarchitectures in 2019 and 2020, representing the architecture step in Intel's Process-Architecture-Optimization model.[2][1][3][4] Ice Lake will be produced on the second generation of Intel's 10 nm process, 10 nm+, becoming Intel's second microarchitecture to be manufactured on the 10 nm process following the limited launch of Cannon Lake in 2018.[2][5][6][7][8]
It is expected that Ice Lake will have in-silicon mitigations for the Meltdown and Spectre hardware vulnerabilities.[9]
Intel released details of Ice Lake during Intel Architecture Day in December of 2018, stating that the Sunny Cove core Ice Lake would be focusing on single-thread performance, new instructions, and scalability improvements. Intel stated that the performance improvements would be achieved by making the core "deeper, wider, and smarter".[10]
The core Ice Lake will be built on, Sunny Cove, will feature 50% increase in the size of L1 data cache, larger L2 cache (size product dependent), larger μop cache, and larger 2nd level TLB. The core has also increased in width, by increasing execution ports from 8 to 10 and by doubling the L1 store bandwidth. Allocation width has also increased from 4 to 5. The paging table for main memory supports a Linear Address space up to 57 bits and a physical address space up to 52 bits, increasing the theoretical addressable memory space to over 4 PB, up from 64 TB.[10]
Ice Lake will feature Intel's Gen11 graphics, increasing the number of execution units (EUs) to 64, from 24 in Gen9.5 graphics, achieving over 1 TFLOPS of compute performance. Each EU supports 7 threads, meaning that the design has 512 concurrent pipelines. Feeding these EUs is a 3 MB L3 cache, a 4x increase from Gen9.5, alongside with the increased memory bandwidth enabled by LPDDR4X on low-power mobile platforms. Gen11 graphics also introduces tile-based rendering and Coarse Pixel Shadowing, Intel's implementation of multi-rate shading. The architecture will also include an all-new HEVC encoder design.[10]
Architecture changes compared to previous 14nm++ Intel microarchitectures
- 10 nm+ transistors
- Generation 11 GPU; includes 64 EU and 512 ALU; 5K and 8K display output[11]
- L1 instruction/data cache: 32KB/48 KiB; L2 cache: 512 KiB[11]
- DisplayPort 1.4a with Display Stream Compression; HDMI 2.0
- Thunderbolt 3 over Type C natively on-die[12][13]
- Six new AVX-512 instructions: VPOPCNTDQ, VBMI2, BITALG, VPCLMULQDQ, GFNI, and VAES
- Integrated support for Wi-Fi 6 (802.11ax)
See also
References
- ^ a b "Intel Officially Reveals Post-8th Generation Core Architecture Code Name: Ice Lake, Built on 10nm+". AnandTech. August 15, 2017.
- ^ a b c Bright, Peter (15 August 2017). "Intel's next generation chip plans: Ice Lake and a slow 10nm transition". Ars Technica. Retrieved 15 August 2017.
- ^ Anton Shilov; Ian Cutress. "Intel Server Roadmap: 14nm Cooper Lake in 2019, 10nm Ice Lake in 2020". Retrieved 2018-09-03.
- ^ Cutress, Ian. "Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'". Retrieved 2018-10-22.
- ^ Dave James (May 30, 2017). "Intel Coffee Lake - 8th Gen Core >30% faster than Kaby Lake and here by the holidays". PCGamesN.
- ^ "Intel teases its Ice Lake & Tiger Lake family, 10nm for 2018 and 2019". Tweaktown.com. 2016-01-21. Retrieved 2016-06-03.
- ^ "What's the Name of Intel's Third 10-Nanometer Chip? - The Motley Fool". The Motley Fool. 2016-01-18. Retrieved 2016-06-03.
- ^ "Cannon Lake stumbles into the market: The IdeaPad 330-15ICN is the first laptop with a 10-nm-CPU". Notebookcheck. Retrieved 2018-10-22.
- ^ https://arstechnica.com/gadgets/2018/01/intel-meltdown-spectre-silicon-fixes-coming-2018-3d-xpoint-ram-not-so-much/
- ^ a b c Cutress, Ian. "Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86". www.anandtech.com. Retrieved 2019-01-14.
- ^ a b "Intel Ice Lake 10nm CPU Benchmark Leak Shows More Cache, Higher Performance". HotHardware. HotHardware. 2018-10-23. Retrieved 2018-11-09.
{{cite news}}: CS1 maint: others (link) - ^ https://newsroom.intel.com/news/intel-takes-steps-enable-thunderbolt-3-everywhere-releases-protocol/#gs.19wo3z
- ^ https://fuse.wikichip.org/news/2318/ice-lake-brings-a-new-cpu-gpu-ipu-and-i-os-to-follow-by-tiger-lake-next-year/