|Computer memory types|
|Early stage NVRAM|
Toshiba developed flash memory from EEPROM (electrically erasable programmable read-only memory) in the early 1980s, and then commercially introduced it to the market in 1987. The two main types of flash memory are named after the NAND and NOR logic gates. The individual flash memory cells exhibit internal characteristics similar to those of the corresponding gates.
While EPROMs had to be completely erased before being rewritten, NAND-type flash memory may be written and read in blocks (or pages) which are generally much smaller than the entire device. NOR-type flash allows a single machine word (byte) to be written – to an erased location – or read independently.
The NAND type is found primarily in memory cards, USB flash drives, solid-state drives (those produced in 2009 or later), and similar products, for general storage and transfer of data. NAND or NOR flash memory is also often used to store configuration data in numerous digital products, a task previously made possible by EEPROM or battery-powered static RAM. One key disadvantage of flash memory is that it can only endure a relatively small number of write cycles in a specific block.
Example applications of both types of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, video games, scientific instrumentation, industrial robotics, and medical electronics. In addition to being non-volatile, flash memory offers fast read access times, although not as fast as static RAM or ROM. Its mechanical shock resistance helps explain its popularity over hard disks in portable devices, as does its high durability, ability to withstand high pressure, temperature and immersion in water, etc.
Although flash memory is technically a type of EEPROM, the term "EEPROM" is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over non-flash EEPROM when writing large amounts of data. As of 2013, flash memory costs much less than byte-programmable EEPROM and had become the dominant memory type wherever a system required a significant amount of non-volatile solid-state storage.
- 1 History
- 2 Principles of operation
- 3 Limitations
- 4 Low-level access
- 5 Distinction between NOR and NAND flash
- 6 Flash file systems
- 7 Capacity
- 8 Transfer rates
- 9 Applications
- 10 Industry
- 11 Flash scalability
- 12 Flash memory manufacturers
- 13 Timeline
- 14 See also
- 15 References
- 16 External links
This section needs additional citations for verification. (July 2010) (Learn how and when to remove this template message)
Flash memory was invented by Fujio Masuoka while working for Toshiba in 1980. According to Toshiba, the name "flash" was suggested by Masuoka's colleague, Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. Masuoka and colleagues presented the invention of NOR flash in 1984, and then NAND flash at the IEEE 1987 International Electron Devices Meeting (IEDM) held in San Francisco.
Toshiba commercially launched NAND flash memory in 1987. Intel Corporation introduced the first commercial NOR type flash chip in 1988. NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older read-only memory (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set-top boxes. Its endurance may be from as little as 100 erase cycles for an on-chip flash memory, to a more typical 10,000 or 100,000 erase cycles, up to 1,000,000 erase cycles. NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash.
NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash; it also has up to 10 times the endurance of NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This makes NAND flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers require byte-level random access. In this regard, NAND flash is similar to other secondary data storage devices, such as hard disks and optical media, and is thus highly suitable for use in mass-storage devices, such as memory cards and solid-state drives (SSD). Flash memory cards and SSDs store data using multiple NAND flash memory chips. The first NAND-based removable memory card format was SmartMedia in 1995, and many others have followed, including:
A new generation of memory card formats, including RS-MMC, miniSD and microSD, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm2, with a thickness of less than 1 mm.
Multi-level cell (MLC) technology stores more than one bit in each memory cell. NEC demonstrated quad-level cell (QLC) technology in 1996, with a 64 Mb flash memory chip storing 2-bit data per cell. STMicroelectronics also demonstrated quad-level cells in 2000, with a 64 Mb NOR flash memory chip. In 2009, Toshiba and SanDisk introduced NAND flash chips with QLC technology storing 4-bit per cell and holding a capacity of 64 Gb. Samsung Electronics introduced triple-level cell (TLC) technology storing 3-bit per cell, and began mass-producing NAND chips with TLC technology in 2010.
3D integrated circuit (3D IC) technology stacks integrated circuit (IC) chips vertically into a single 3D IC chip package. Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16 GB THGAM embedded NAND flash memory chip, which was manufactured with eight stacked 2 GB NAND flash chips. In September 2007, Hynix Semiconductor (now SK Hynix) introduced 24-layer 3D IC technology, with a 16 GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process. Toshiba also used an eight-layer 3D IC for their 32 GB THGBM flash chip in 2008. In 2010, Toshiba used a 16-layer 3D IC for their 128 GB THGBM2 flash chip, which was manufactured with 16 stacked 8 GB chips. In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in mobile devices.
3D V-NAND (vertical NAND) technology stacks NAND flash memory cells vertically within a chip using 3D charge trap flash (CTP) technology. 3D V-NAND technology was first announced by Toshiba in 2007, and was first commercially released by Samsung Electronics in 2013.
As of August 2017, microSD cards with a capacity up to 400 GB (400 billion bytes) are available. The same year, Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512 GB KLUFG8R1EM flash memory chip with eight stacked 64-layer V-NAND chips. In 2019, Samsung produced a 1 TB flash chip, with eight stacked 96-layer V-NAND chips and with QLC technology.
Principles of operation
Flash memory stores information in an array of memory cells made from floating-gate transistors. In single-level cell (SLC) devices, each cell stores only one bit of information. Multi-level cell (MLC) devices, including triple-level cell (TLC) devices, can store more than one bit per cell.
In flash memory, each memory cell resembles a standard metal-oxide-semiconductor field-effect transistor (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as an electrical switch in which current flows between two terminals (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this, there is the FG insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge screens the electric field from the CG, thus, increasing the threshold voltage (VT1) of the cell. This means that now a higher voltage (VT2) must be applied to the CG to make the channel conductive. In order to read a value from the transistor, an intermediate voltage between the threshold voltages (VT1 & VT2) is applied to the CG. If the channel conducts at this intermediate voltage, the FG must be uncharged (if it was charged, we would not get conduction because the intermediate voltage is less than VT2), and hence, a logical "1" is stored in the gate. If the channel does not conduct at the intermediate voltage, it indicates that the FG is charged, and hence, a logical "0" is stored in the gate. The presence of a logical "0" or "1" is sensed by determining whether there is current flowing through the transistor when the intermediate voltage is asserted on the CG. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
The process of moving electrons from the control gate and into the floating gate is called Fowler–Nordheim tunneling, and it fundamentally changes the characteristics of the cell by increasing the MOSFET’s threshold voltage. This, in turn, changes the drain-source current that flows through the transistor for a given gate voltage, which is ultimately used to encode a binary value. The Fowler-Nordheim tunneling effect is reversible, so electrons can be added to or removed from the floating gate, processes traditionally known as writing and erasing. 
Internal charge pumps
Despite the need for relatively high programming and erasing voltages, virtually all flash chips today require only a single supply voltage and produce the high voltages using on-chip charge pumps.
Over half the energy used by a 1.8 V NAND flash chip is lost in the charge pump itself. Since boost converters are inherently more efficient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all the early flash chips, driving the high Vpp voltage for all flash chips in a SSD with a single shared external boost converter.
In spacecraft and other high-radiation environments, the on-chip charge pump is the first part of the flash chip to fail, although flash memories will continue to work – in read-only mode – at much higher radiation levels.
In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.
A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:
- an elevated on-voltage (typically >5 V) is applied to the CG
- the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)
- the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection.
To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through quantum tunneling. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together. Programming of NOR cells, however, generally can be performed one byte or word at a time.
NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors' VT). These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash.
Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. Execute-in-place applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash.
To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors.
Writing and erasing
NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.
The architecture of NAND Flash means that data can be read and programmed in pages, typically between 4 KiB and 16 KiB in size, but can only be erased at the level of entire blocks consisting of multiple pages and MB in size. When a block is erased all the cells are logically set to 1. Data can only be programmed in one pass to a page in a block that was erased. Any cells that have been set to 0 by programming can only be reset to 1 by erasing the entire block. This means that before new data can be programmed into a page that already contains data, the current contents of the page plus the new data must be copied to a new, erased page. If a suitable page is available, the data can be written to it immediately. If no erased page is available, a block must be erased before copying the data to a page in that block. The old page is then marked as invalid and is available for erasing and reuse. 
Vertical NAND (V-NAND) memory stacks memory cells vertically and uses a charge trap flash architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells. It is also known as 3D NAND or BiCS Flash. 3D NAND was first announced by Toshiba in 2007. V-NAND was first commercially manufactured by Samsung Electronics in 2013.
V-NAND uses a charge trap flash geometry (which was commercially introduced in 2002 by AMD and Fujitsu) that stores charge on an embedded silicon nitride film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form.
The hierarchical structure of NAND Flash starts at a cell level which establishes strings, then pages, blocks, planes and ultimately a die. A string is a series of connected NAND cells in which the source of one cell is connected to the drain of the next one. Depending on the NAND technology, a string typically consists of 32 to 128 NAND cells. Strings are organised into pages which are then organised into blocks in which each string is connected to a separate line called a bitline (BL) All cells with the same position in the string are connected through the control gates by a wordline (WL) A plane contains a certain number of blocks that are connected through the same BL. A Flash die consists of one or more planes, and the peripheral circuitry that is needed to perform all the read/ write/ erase operations.
An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.
Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND flash memory is configured.
Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers.
The next step is to form a cylindrical hole through these layers. In practice, a 128 Gibit V-NAND chip with 24 layers of memory cells requires about 2.9 billion such holes. Next, the hole's inner surface receives multiple coatings, first silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally, the hole is filled with conducting (doped) polysilicon.
As of 2013, V-NAND flash architecture allows read and write operations twice as fast as conventional NAND and can last up to 10 times as long, while consuming 50 percent less power. They offer comparable physical bit density using 10-nm lithography but may be able to increase bit density by up to two orders of magnitude.
One limitation of flash memory is that, although it can be read or programmed a byte or a word at a time in a random access fashion, it can be erased only a block at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations but does not offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written values. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Essentially, erasure sets all bits to 1, and programming can only clear bits to 0. Some file systems designed for flash devices make use of this rewrite capability, for example Yaffs1, to represent sector metadata. Other flash file systems, such as YAFFS2, never make use of this "rewrite" capability -- they do a lot of extra work to meet a "write once rule".
Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique may need to be modified for multi-level cell devices, where one memory cell holds more than one bit.
Common flash devices such as USB flash drives and memory cards provide only a block-level interface, or flash translation layer (FTL), which writes to a different cell each time to wear-level the device. This prevents incremental writing within a block; however, it does help the device from being prematurely worn out by intensive write patterns.
Another limitation is that flash memory has a finite number of program – erase cycles (typically written as P/E cycles). Most commercially available flash products are guaranteed to withstand around 100,000 P/E cycles before the wear begins to deteriorate the integrity of the storage. Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on 17 December 2008.
The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND devices), or to all blocks (as in NOR). This effect is mitigated in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear leveling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, these wear out management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high-reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and routers, which are programmed only once or at most a few times during their lifetimes.
In December 2012, Taiwanese engineers from Macronix revealed their intention to announce at the 2012 IEEE International Electron Devices Meeting that they had figured out how to improve NAND flash storage read/write cycles from 10,000 to 100 million cycles using a "self-healing" process that used a flash chip with "onboard heaters that could anneal small groups of memory cells." The built-in thermal annealing was to replace the usual erase cycle with a local high temperature process that not only erased the stored charge, but also repaired the electron-induced stress in the chip, giving write cycles of at least 100 million. The result was to be a chip that could be erased and rewritten over and over, even when it should theoretically break down. As promising as Macronix’s breakthrough might have been for the mobile industry, however, there were no plans for a commercial product to be released any time in the near future.
The method used to read NAND flash memory can cause nearby cells in the same memory block to change over time (become programmed). This is known as read disturb. The threshold number of reads is generally in the hundreds of thousands of reads between intervening erase operations. If reading continually from one cell, that cell will not fail but rather one of the surrounding cells on a subsequent read. To avoid the read disturb problem the flash controller will typically count the total number of reads to a block since the last erase. When the count exceeds a target limit, the affected block is copied over to a new block, erased, then released to the block pool. The original block is as good as new after the erase. If the flash controller does not intervene in time, however, a read disturb error will occur with possible data loss if the errors are too numerous to correct with an error-correcting code.
Most flash ICs come in ball grid array (BGA) packages, and even the ones that do not are often mounted on a PCB next to other BGA packages. After PCB Assembly, boards with BGA packages are often X-rayed to see if the balls are making proper connections to the proper pad, or if the BGA needs rework. These X-rays can erase programmed bits in a flash chip (convert programmed "0" bits into erased "1" bits). Erased bits ("1" bits) are not affected by X-rays.
The low-level interface to flash memory chips differs from those of other memory types such as DRAM, ROM, and EEPROM, which support bit-alterability (both zero to one and one to zero) and random access via externally accessible address buses.
NOR memory has an external address bus for reading and programming. For NOR memory, reading and programming are random-access, and unlocking and erasing are block-wise. For NAND memory, reading and programming are page-wise, and unlocking and erasing are block-wise.
Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly from the NOR flash without needing to be copied into RAM first. NOR flash may be programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256 KiB.
Bad block management is a relatively new feature in NOR chips. In older NOR devices not supporting bad block management, the software or device driver controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.
The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, special Common Flash Memory Interface (CFI) commands allow the device to identify itself and its critical operating parameters.
Besides its use as random-access ROM, NOR flash can also be used as a storage device, by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR flash chips typically have slow write speeds, compared with NAND flash.
NAND flash architecture was introduced by Toshiba in 1989. These memories are accessed much like block devices, such as hard disks. Each block consists of a number of pages. The pages are typically 512, 2,048 or 4,096 bytes in size. Associated with each page are a few bytes (typically 1/32 of the data size) that can be used for storage of an error correcting code (ECC) checksum.
Typical block sizes include:
- 32 pages of 512+16 bytes each for a block size (effective) of 16 KB
- 64 pages of 2,048+64 bytes each for a block size of 128 KB
- 64 pages of 4,096+128 bytes each for a block size of 256 KB
- 128 pages of 4,096+128 bytes each for a block size of 512 KB.
While reading and programming is performed on a page basis, erasure can only be performed on a block basis.
NAND devices also require bad block management by the device driver software or by a separate controller chip. SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.
NAND relies on ECC to compensate for bits that may spontaneously fail during normal device operation. A typical ECC will correct a one-bit error in each 2048 bits (256 bytes) using 22 bits of ECC, or a one-bit error in each 4096 bits (512 bytes) using 24 bits of ECC. If the ECC cannot correct the error during read, it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to program or erase and mark them bad. The data is then written to a different, good block, and the bad block map is updated.
Hamming codes are the most commonly used ECC for SLC NAND flash. Reed-Solomon codes and Bose-Chaudhuri-Hocquenghem codes are commonly used ECC for MLC NAND flash. Some MLC NAND flash chips internally generate the appropriate BCH error correction codes.
Most NAND devices are shipped from the factory with some bad blocks. These are typically marked according to a specified bad block marking strategy. By allowing some bad blocks, the manufacturers achieve far higher yields than would be possible if all blocks had to be verified good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.
When executing software from NAND memories, virtual memory strategies are often used: memory contents must first be paged or copied into memory-mapped RAM and executed there (leading to the common combination of NAND + RAM). A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a non-volatile data storage area.
NAND sacrifices the random-access and execute-in-place advantages of NOR. NAND is best suited to systems requiring high capacity data storage. It offers higher densities, larger capacities, and lower cost. It has faster erases, sequential writes, and sequential reads.
A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low-level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0 was released on 28 December 2006. It specifies:
- a standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
- a standard command set for reading, writing, and erasing NAND flash chips
- a mechanism for self-identification (comparable to the serial presence detection feature of SDRAM memory modules)
Two major flash device manufacturers, Toshiba and Samsung, have chosen to use an interface of their own design known as Toggle Mode (and now Toggle V2.0). This interface isn't pin-to-pin compatible with the ONFI specification. The result is a product designed for one vendor's devices may not be able to use another vendor's devices.
A group of vendors, including Intel, Dell, and Microsoft, formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group. The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus.
Distinction between NOR and NAND flash
NOR and NAND flash differ in two important ways:
- the connections of the individual memory cells are different
- the interface provided for reading and writing the memory is different (NOR allows random-access for reading, NAND allows only page access)
These two are linked by the design choices made in the development of NAND flash. A goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks.
NOR and NAND flash get their names from the structure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a CMOS NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash. It does not, by itself, prevent NAND cells from being read and programmed individually.
Each NOR flash cell is larger than a NAND flash cell – 10 F2 vs 4 F2 – even when using exactly the same semiconductor device fabrication and so each transistor, contact, etc. is exactly the same size – because NOR flash cells require a separate metal contact for each cell.
When NOR flash was developed, it was envisioned as a more economical and conveniently rewritable ROM than contemporary EPROM and EEPROM memories. Thus random-access reading circuitry was necessary. However, it was expected that NOR flash ROM would be read much more often than written, so the write circuitry included was fairly slow and could erase only in a block-wise fashion. On the other hand, applications that use flash as a replacement for disk drives do not require word-level write address, which would only add to the complexity and cost unnecessarily.
Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells (assuming the same CMOS process resolution, for example, 130 nm, 90 nm, or 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace mechanical hard disks, not to replace ROMs.
|Main application||File storage||Code execution|
|Cost per bit||Better|
The write endurance of SLC floating-gate NOR flash is typically equal to or greater than that of NAND flash, while MLC NOR and NAND flash have similar endurance capabilities. Examples of endurance cycle ratings listed in datasheets for NAND and NOR flash, as well as in storage devices using flash memory, are provided.
|Type of flash memory||Endurance rating (erases per block)||Example(s) of flash memory or storage device|
|SLC NAND||100,000||Samsung OneNAND KFW4G16Q2M, Toshiba SLC NAND Flash chips|
|MLC NAND||5,000 to 10,000 for medium-capacity applications;
1,000 to 3,000 for high-capacity applications
|Samsung K9G8G08U0M (Example for medium-capacity applications), Memblaze PBlaze4 |
|TLC NAND||1,000||Samsung SSD 840|
|3D MLC NAND||6,000 to 40,000||Samsung SSD 850 PRO, Samsung SSD 845DC PRO|
|3D TLC NAND||1,000 to 3,000||Samsung SSD 850 EVO, Samsung SSD 845DC EVO, Crucial MX300，Memblaze PBlaze5 900, Memblaze PBlaze5 700, Memblaze PBlaze5 910/916,Memblaze PBlaze5 510/516 |
|3D QLC NAND||100 to 1,000||Samsung SSD 860 QVO SATA, Intel SSD 660p, Samsung SSD 980 QVO NVMe, Micron 5210 ION, Samsung SSD BM991 NVMe|
|SLC (floating-gate) NOR||100,000 to 1,000,000||Numonyx M58BW (Endurance rating of 100,000 erases per block);|
Spansion S29CD016J (Endurance rating of 1,000,000 erases per block)
|MLC (floating-gate) NOR||100,000||Numonyx J3 flash|
In order to compute the longevity of the NAND flash, one must account for the size of the memory chip, the type of memory (e.g. SLC/MLC/TLC), and use pattern.
Flash file systems
Because of the particular characteristics of flash memory, it is best used with either a controller to perform wear leveling and error correction or specifically designed flash file systems, which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is the following: when the flash store is to be updated, the file system will write a new copy of the changed data to a fresh block, remap the file pointers, then erase the old block later when it has time.
In practice, flash file systems are used only for memory technology devices (MTDs), which are embedded flash memories that do not have a controller. Removable flash memory cards and USB flash drives have built-in controllers to perform wear leveling and error correction so use of a specific flash file system does not add any benefit.
Multiple chips are often arrayed to achieve higher capacities for use in consumer electronic devices such as multimedia players or GPSs. The capacity of flash chips generally follows Moore's Law because they are manufactured with many of the same integrated circuits techniques and equipment.
Consumer flash storage devices typically are advertised with usable sizes expressed as a small integer power of two (2, 4, 8, etc.) and a designation of megabytes (MB) or gigabytes (GB); e.g., 512 MB, 8 GB. This includes SSDs marketed as hard drive replacements, in accordance with traditional hard drives, which use decimal prefixes. Thus, an SSD marked as "64 GB" is at least 64 × 10003 bytes (64 GB). Most users will have slightly less capacity than this available for their files, due to the space taken by file system metadata.
The flash memory chips inside them are sized in strict binary multiples, but the actual total capacity of the chips is not usable at the drive interface. It is considerably larger than the advertised capacity in order to allow for distribution of writes (wear leveling), for sparing, for error correction codes, and for other metadata needed by the device's internal firmware.
In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using multi-level cell (MLC) technology, capable of storing two bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world’s first 2 GB chip.
In March 2006, Samsung announced flash hard drives with a capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a 40 nm manufacturing process. In January 2008, SanDisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.
More recent flash drives (as of 2012) have much greater capacities, holding 64, 128, and 256 GB.
A joint development at Intel and Micron will allow the production of 32-layer 3.5 terabyte (TB) NAND flash sticks and 10 TB standard-sized SSDs. The device includes 5 packages of 16 × 48 GB TLC dies, using a floating gate cell design.
Flash chips continue to be manufactured with capacities under or around 1 MB, e.g., for BIOS-ROMs and embedded applications.
In July 2016, Samsung announced the 4TB Samsung 850 EVO which utilizes their 256 Gb 48-layer TLC 3D V-NAND. In August 2016, Samsung announced a 32 TB 2.5-inch SAS SSD based on their 512 Gb 64-layer TLC 3D V-NAND. Further, Samsung expects to unveil SSDs with up to 100 TB of storage by 2020.
Flash memory devices are typically much faster at reading than writing. Performance also depends on the quality of storage controllers which become more critical when devices are partially full. Even when the only change to manufacturing is die-shrink, the absence of an appropriate controller can result in degraded speeds.
Serial flash is a small, low-power flash memory that provides only serial access to the data - rather than addressing individual bytes, the user reads or writes large contiguous groups of bytes in the address space serially. Serial Peripheral Interface Bus (SPI) is a typical protocol for accessing the device. When incorporated into an embedded system, serial flash requires fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.
There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:
- Many ASICs are pad-limited, meaning that the size of the die is constrained by the number of wire bond pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a wafer, and thus reduces the cost per die.
- Reducing the number of external pins also reduces assembly and packaging costs. A serial device may be packaged in a smaller and simpler package than a parallel device.
- Smaller and lower pin-count packages occupy less PCB area.
- Lower pin-count devices simplify PCB routing.
There are two major SPI flash types. The first type is characterized by small pages and one or more internal SRAM page buffers allowing a complete page to be read to the buffer, partially modified, and then written back (for example, the Atmel AT45 DataFlash or the Micron Technology Page Erase NOR Flash). The second type has larger sectors. The smallest sectors typically found in an SPI flash are 4 kB, but they can be as large as 64 kB. Since the SPI flash lacks an internal SRAM buffer, the complete page must be read out and modified before being written back, making it slow to manage. SPI flash is cheaper than DataFlash and is therefore a good choice when the application is code shadowing.
The two types are not easily exchangeable, since they do not have the same pinout, and the command sets are incompatible.
With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to. Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns. Because of this, it is often desirable to shadow code stored in flash into RAM; that is, the code is copied from flash into RAM before execution, so that the CPU may access it at full speed. Device firmware may be stored in a serial flash device, and then copied into SDRAM or SRAM when the device is powered-up. Using an external serial flash device rather than on-chip flash removes the need for significant process compromise (a manufacturing process that is good for high-speed logic is generally not good for flash and vice versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Typical applications for serial flash include storing firmware for hard drives, Ethernet controllers, DSL modems, wireless network devices, etc.
Flash memory as a replacement for hard drives
One more recent application for flash memory is as a replacement for hard disks. Flash memory does not have the mechanical limitations and latencies of hard drives, so a solid-state drive (SSD) is attractive when considering speed, noise, power consumption, and reliability. Flash drives are gaining traction as mobile device secondary storage devices; they are also used as substitutes for hard drives in high-performance desktop computers and some servers with RAID and SAN architectures.
There remain some aspects of flash-based SSDs that make them unattractive. The cost per gigabyte of flash memory remains significantly higher than that of hard disks. Also flash memory has a finite number of P/E cycles, but this seems to be currently under control since warranties on flash-based SSDs are approaching those of current hard drives. In addition, deleted files on SSDs can remain for an indefinite period of time before being overwritten by fresh data; erasure or shred techniques or software that work well on magnetic hard disk drives have no effect on SSDs, compromising security and forensic examination.
In May 2006, Samsung Electronics announced two flash-memory based PCs, the Q1-SSD and Q30-SSD were expected to become available in June 2006, both of which used 32 GB SSDs, and were at least initially available only in South Korea. The Q1-SSD and Q30-SSD launch was delayed and finally shipped in late August 2006. 
The first flash-memory based PC to become available was the Sony Vaio UX90, announced for pre-order on 27 June 2006 and began shipping in Japan on 3 July 2006 with a 16Gb flash memory hard drive.  In late September 2006 Sony upgraded the flash-memory in the Vaio UX90 to 32Gb. 
A solid-state drive was offered as an option with the first MacBook Air introduced in 2008, and from 2010 onwards, all models shipped with an SSD. Starting in late 2011, as part of Intel's Ultrabook initiative, an increasing number of ultra-thin laptops are being shipped with SSDs standard.
There are also hybrid techniques such as hybrid drive and ReadyBoost that attempt to combine the advantages of both technologies, using flash as a high-speed non-volatile cache for files on the disk that are often referenced, but rarely modified, such as application and operating system executable files.
Flash memory as RAM
Archival or long-term storage
It is unclear how long flash memory will persist under archival conditions – i.e., benign temperature and humidity with infrequent access with or without prophylactic rewrite. Datasheets of Atmel's flash-based "ATmega" microcontrollers typically promise retention times of 20 years at 85 °C (185 °F) and 100 years at 25 °C (77 °F).
An article from CMU in 2015 writes that "Today's flash devices, which do not require flash refresh, have a typical retention age of 1 year at room temperature." And that temperature can lower the retention time exponentially. The phenomenon can be modeled by the Arrhenius equation.
Some FPGAs are based on flash configuration cells that are used directly as (programmable) switches to connect internal elements together, using the same kind of floating-gate transistor as the flash data storage cells in data storage devices.
One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. Other sources put the flash memory market at a size of more than US$20 billion in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market. In 2012, the market was estimated at $26.8 billion.
Due to its relatively simple structure and high demand for higher capacity, NAND flash memory is the most aggressively scaled technology among electronic devices. The heavy competition among the top few manufacturers only adds to the aggressiveness in shrinking the design rule or process technology node. While the expected shrink timeline is a factor of two every three years per original version of Moore's law, this has recently been accelerated in the case of NAND flash to a factor of two every two years.
|ITRS or company||2010||2011||2012||2013||2014||2015||2016||2017||2018|
|ITRS Flash Roadmap 2011||32 nm||22 nm||20 nm||18 nm||16 nm|
|Updated ITRS Flash Roadmap||17 nm||15 nm||14 nm|
(Samsung 3D NAND)
|35–20 nm||27 nm||21 nm
19–10 nm (MLC, TLC)
|16–10 nm||12–10 nm||12–10 nm|
|Micron, Intel||34–25 nm||25 nm||20 nm
(MLC + HKMG)
|16 nm||16 nm
|Toshiba, WD (SanDisk)||43–32 nm
24 nm (Toshiba)
|24 nm||19 nm
|15 nm||15 nm
|12 nm |
|SK Hynix||46–35 nm||26 nm||20 nm (MLC)||16 nm||16 nm||16 nm||12 nm||12 nm|
As the feature size of flash memory cells reaches the 15-16 nm minimum limit, further flash density increases will be driven by TLC (3 bits/cell) combined with vertical stacking of NAND memory planes. The decrease in endurance and increase in uncorrectable bit error rates that accompany feature size shrinking can be compensated by improved error correction mechanisms. Even with these advances, it may be impossible to economically scale flash to smaller and smaller dimensions as the number of electron holding capacity reduces. Many promising new technologies (such as FeRAM, MRAM, PMC, PCM, ReRAM, and others) are under investigation and development as possible more scalable replacements for flash.
Flash memory manufacturers
The following are the largest NAND flash memory manufacturers, as of the first quarter of 2019.
- Samsung – 29.9%
- Toshiba – 20.2%
- Micron Technology – 16.5%
- Western Digital (SanDisk) – 14.9%
- SK Hynix – 9.5%
- Intel – 8.5%
|Date of introduction||Chip name||Capacity (bits)||Flash type||Cell type||Manufacturer(s)||Process||Area||Ref|
|1985||?||256 kb||NOR||SLC||Toshiba||2,000 nm||?|||
|1989||?||1 Mb||NOR||SLC||Seeq, Intel||?||?|||
|1989||?||4 Mb||NAND||SLC||Toshiba||1,000 nm||?|||
|1991||?||16 Mb||NOR||SLC||Mitsubishi||600 nm||?|||
|1993||DD28F032SA||32 Mb||NOR||SLC||Intel||?||280 mm²|||
|1994||?||64 Mb||NOR||SLC||NEC||400 nm||?|||
|1995||?||16 Mb||DINOR||SLC||Mitsubishi, Hitachi||?||?|||
|1995||?||32 Mb||NAND||SLC||Hitachi, Samsung, Toshiba||?||?|||
|1996||?||64 Mb||NAND||SLC||Hitachi, Mitsubishi||400 nm||?|||
|1996||?||64 Mb||NAND||QLC||NEC||400 nm||?|||
|1996||?||128 Mb||NAND||SLC||Samsung, Hitachi||?||?|
|1997||?||32 Mb||NOR||SLC||Intel, Sharp||400 nm||?|||
|1997||?||32 Mb||NAND||SLC||AMD, Fujitsu||350 nm||?|
|1999||?||256 Mb||NAND||SLC||Toshiba||250 nm||?|||
|1999||?||256 Mb||NAND||MLC||Hitachi||250 nm||?|
|2000||?||32 Mb||NOR||SLC||Toshiba||250 nm||?|
|2000||?||64 Mb||NOR||QLC||STMicroelectronics||180 nm||?|
|2001||?||1 Gb||NAND||MLC||Toshiba, SanDisk||160 nm||?|||
|2002||?||512 Mb||NROM||MLC||Saifun||170 nm||?|||
|2002||?||2 Gb||NAND||SLC||Samsung, Toshiba||?||?|||
|2003||?||128 Mb||NOR||MLC||Intel||130 nm||?|||
|2003||?||1 Gb||NAND||MLC||Hitachi||130 nm||?|||
|2004||?||8 Gb||NAND||SLC||Samsung||60 nm||?|||
|2005||?||16 Gb||NAND||SLC||Samsung||50 nm||?|||
|2006||?||32 Gb||NAND||SLC||Samsung||40 nm||?|||
|April 2007||THGAM||128 Gb||Stacked NAND||SLC||Toshiba||56 nm||252 mm²|||
|September 2007||?||128 Gb||Stacked NAND||SLC||Hynix||?||?|||
|2008||THGBM||256 Gb||Stacked NAND||SLC||Toshiba||43 nm||353 mm²|||
|2009||?||32 Gb||NAND||TLC||Toshiba||32 nm||113 mm²|||
|2009||?||64 Gb||NAND||QLC||Toshiba, SanDisk||43 nm||?|||
|2010||?||64 Gb||NAND||SLC||Hynix||20 nm||?|||
|2010||?||64 Gb||NAND||TLC||Samsung||20 nm||?|||
|2010||THGBM2||1 Tb||Stacked NAND||QLC||Toshiba||32 nm||374 mm²|||
|2011||KLMCG8GE4A||512 Gb||Stacked NAND||MLC||Samsung||?||192 mm²|||
|2013||?||?||NAND||SLC||SK Hynix||16 nm||?|||
|2013||?||128 Gb||V-NAND||TLC||Samsung||10 nm||?|||
|2017||KLUFG8R1EM||4 Tb||Stacked V-NAND||TLC||Samsung||?||150 mm²|||
|2018||?||1.33 Tb||V-NAND||QLC||Toshiba||?||158 mm²|||
|2019||?||1 Tb||V-NAND||TLC||SK Hynix||?||?|||
|2019||eUFS (1 TB)||8 Tb||Stacked V-NAND||QLC||Samsung||?||150 mm²|||
- List of flash file systems
- microSDXC (up to 2 TB)
- Open NAND Flash Interface Working Group
- USB flash drive security
- Write amplification
- "1987: Toshiba Launches NAND Flash". eWeek. 11 April 2012. Retrieved 20 June 2019.
- "A Flash Storage Technical and Economic Primer". flashstorage.com. 30 March 2015. Archived from the original on 20 July 2015.
- Mittal, Sparsh; Vetter, Jeffrey S. (2016). "A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems". IEEE Transactions on Parallel and Distributed Systems. 27 (5): 1537–1550. doi:10.1109/TPDS.2015.2442980.
- Fulford, Benjamin (24 June 2002). "Unsung hero". Forbes. Archived from the original on 3 March 2008. Retrieved 18 March 2008.
- US 4531203 Fujio Masuoka
- Semiconductor memory device and method for manufacturing the same
- "NAND Flash Memory: 25 Years of Invention, Development - Data Storage - News & Reviews - eWeek.com". eweek.com.
- "Toshiba: Inventor of Flash Memory". Toshiba. Retrieved 20 June 2019.
- Masuoka, F.; Asano, M.; Iwahashi, H.; Komuro, T.; Tanaka, S. (December 1984). "A new flash E2PROM cell using triple polysilicon technology". 1984 International Electron Devices Meeting: 464–467. doi:10.1109/IEDM.1984.190752.
- Masuoka, F.; Momodomi, M.; Iwata, Y.; Shirota, R. (1987). "New ultra high density EPROM and flash EEPROM with NAND structure cell". Electron Devices Meeting, 1987 International. IEDM 1987. IEEE. doi:10.1109/IEDM.1987.191485.
- "1971: Reusable semiconductor ROM introduced". Computer History Museum. Retrieved 19 June 2019.
- Tal, Arie (February 2002). "NAND vs. NOR flash technology: The designer should weigh the options when using flash memory". Archived from the original on 28 July 2010. Retrieved 31 July 2010.
- "H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398F-ZTATTM Hardware Manual, Section 19.6.1" (PDF). Renesas. October 2004. Retrieved 23 January 2012.
The flash memory can be reprogrammed up to 100 times.
- "AMD DL160 and DL320 Series Flash: New Densities, New Features" (PDF). AMD. July 2003. Archived (PDF) from the original on 24 September 2015. Retrieved 13 November 2014.
The devices offer single-power-supply operation (2.7 V to 3.6 V), sector architecture, Embedded Algorithms, high performance, and a 1,000,000 program/erase cycle endurance guarantee.
- James, Dick (2014). "3D ICs in the real world". 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014): 113–119. doi:10.1109/ASMC.2014.6846988.
- "Memory". STOL (Semiconductor Technology Online). Retrieved 25 June 2019.
- "Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology". Toshiba. 11 February 2009. Retrieved 21 June 2019.
- "SanDisk ships world's first memory cards with 64 gigabit X4 NAND flash". SlashGear. 13 October 2009. Retrieved 20 June 2019.
- "History". Samsung Electronics. Samsung. Retrieved 19 June 2019.
- "TOSHIBA COMMERCIALIZES INDUSTRY'S HIGHEST CAPACITY EMBEDDED NAND FLASH MEMORY FOR MOBILE CONSUMER PRODUCTS". Toshiba. 17 April 2007. Retrieved 23 November 2010.
- "Hynix Surprises NAND Chip Industry". Korea Times. 5 September 2007. Retrieved 8 July 2019.
- "Toshiba Launches the Largest Density Embedded NAND Flash Memory Devices". Toshiba. 7 August 2008. Retrieved 21 June 2019.
- "Toshiba Launches Industry's Largest Embedded NAND Flash Memory Modules". Toshiba. 17 June 2010. Retrieved 21 June 2019.
- "Toshiba announces new "3D" NAND flash technology". Engadget. 12 June 2007. Retrieved 10 July 2019.
- "Samsung Introduces World's First 3D V-NAND Based SSD for Enterprise Applications | Samsung | Samsung Semiconductor Global Website". www.samsung.com.
- Clarke, Peter. "Samsung Confirms 24 Layers in 3D NAND". EETimes.
- SanDisk®. "Western Digital® Breaks Boundaries with World's Highest-Capacity microSD™ Card". www.sandisk.com. Archived from the original on 1 September 2017. Retrieved 2 September 2017.
- Bradley, Tony. "Expand Your Mobile Storage With New 400GB microSD Card From SanDisk". Forbes. Archived from the original on 1 September 2017. Retrieved 2 September 2017.
- Shilov, Anton (5 December 2017). "Samsung Starts Production of 512 GB UFS NAND Flash Memory: 64-Layer V-NAND, 860 MB/s Reads". AnandTech. Retrieved 23 June 2019.
- Manners, David (30 January 2019). "Samsung makes 1TB flash eUFS module". Electronics Weekly. Retrieved 23 June 2019.
- Tallis, Billy (17 October 2018). "Samsung Shares SSD Roadmap for QLC NAND And 96-layer 3D NAND". AnandTech. Retrieved 27 June 2019.
- Basinger, Matt (18 January 2007), PSoC Designer Device Selection Guide (PDF), AN2209, archived from the original (PDF) on 31 October 2009,
- https://www.hyperstone.com/en/Solid-State-bit-density-and-the-Flash-Memory-Controller-1235,12728.html, Solid State bit density, and the Flash Memory Controller, Retrieved 29. May 2018
- Yasufuku, Tadashi; Ishida, Koichi; Miyamoto, Shinji; Nakai, Hiroto; Takamiya, Makoto; Sakurai, Takayasu; Takeuchi, Ken (2009), Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09, pp. 87–92, doi:10.1145/1594233.1594253, ISBN 9781605586847, archived from the original on 5 March 2016 (abstract).
- Micheloni, Rino; Marelli, Alessia; Eshghi, Kam (2012), Inside Solid State Drives (SSDs), ISBN 9789400751460, archived from the original on 9 February 2017
- Micheloni, Rino; Crippa, Luca (2010), Inside NAND Flash Memories, ISBN 9789048194315, archived from the original on 9 February 2017 In particular, pp 515-536: K. Takeuchi. "Low power 3D-integrated SSD"
- Mozel, Tracey (2009), CMOSET Fall 2009 Circuits and Memories Track Presentation Slides, ISBN 9781927500217, archived from the original on 9 February 2017
- Tadashi Yasufuku et al., "Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories" Archived 4 February 2016 at the Wayback Machine. 2010.
- Hatanaka, T. and Takeuchi, K. "4-times faster rising VPASS (10V), 15% lower power VPGM (20V), wide output voltage range voltage generator system for 4-times faster 3D-integrated solid-state drives" Archived 13 April 2016 at the Wayback Machine. 2011.
- Takeuchi, K., "Low power 3D-integrated Solid-State Drive (SSD) with adaptive voltage generator" Archived 13 April 2016 at the Wayback Machine. 2010.
- Ishida, K. et al., "1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD" Archived 13 April 2016 at the Wayback Machine. 2011.
- A. H. Johnston, "Space Radiation Effects in Advanced Flash Memories" Archived 4 March 2016 at the Wayback Machine. NASA Electronic Parts and Packaging Program (NEPP). 2001. "... internal transistors used for the charge pump and erase/write control have much thicker oxides because of the requirement for high voltage. This causes flash devices to be considerably more sensitive to total dose damage compared to other ULSI technologies. It also implies that write and erase functions will be the first parameters to fail from total dose. ... Flash memories will work at much higher radiation levels in the read mode. ... The charge pumps that are required to generate the high voltage for erasing and writing are usually the most sensitive circuit functions, usually failing below 10 krad(SI)."
- Zitlaw, Cliff. "The Future of NOR Flash Memory". Memory Designline. UBM Media. Retrieved 3 May 2011.
- https://www.hyperstone.com/en/NAND-Flash-controllers-The-key-to-endurance-and-reliability-1256,12728.html NAND Flash Controllers - The key to endurance and reliability, Retrieved 7. June 2018
- "Samsung moves into mass production of 3D flash memory". Gizmag.com. Archived from the original on 27 August 2013. Retrieved 27 August 2013.
- "Samsung Electronics Starts Mass Production of Industry First 3-bit 3D V-NAND Flash Memory". news.samsung.com.
- "Samsung V-NAND technology" (PDF). Samsung Electronics. September 2014. Retrieved 27 March 2016.
- "Samsung produces first 3D NAND, aims to boost densities, drive lower cost per GB". ExtremeTech. 6 August 2013. Retrieved 4 July 2019.
- "AVR105: Power Efficient High Endurance Parameter Storage in Flash Memory". p. 3
- Jonathan Thatcher, Fusion-io; Tom Coughlin, Coughlin Associates; Jim Handy, Objective-Analysis; Neal Ekker, Texas Memory Systems (April 2009). "NAND Flash Solid State Storage for the Enterprise, An In-depth Look at Reliability" (PDF). Solid State Storage Initiative (SSSI) of the Storage Network Industry Association (SNIA). Archived (PDF) from the original on 14 October 2011. Retrieved 6 December 2011.CS1 maint: Multiple names: authors list (link)
- "Micron Collaborates with Sun Microsystems to Extend Lifespan of Flash-Based Storage, Achieves One Million Write Cycles" (Press release). Micron Technology, Inc. 17 December 2008. Archived from the original on 4 March 2016.
- "Taiwan engineers defeat limits of flash memory". phys.org. Archived from the original on 9 February 2016.
- "Flash memory made immortal by fiery heat". theregister.co.uk. Archived from the original on 13 September 2017.
- "Flash memory breakthrough could lead to even more reliable data storage". news.yahoo.com. Archived from the original on 21 December 2012.
- "TN-29-17 NAND Flash Design and Use Considerations Introduction" (PDF). Micron. April 2010. Archived (PDF) from the original on 12 December 2015. Retrieved 29 July 2011.
- Kawamatus, Tatsuya. "Technology For Managing NAND Flash" (PDF). Hagiwara sys-com co., LTD. Archived from the original (PDF) on 15 May 2018. Retrieved 15 May 2018.
- Cooke, Jim (August 2007). "The Inconvenient Truths of NAND Flash Memory" (PDF). Flash Memory Summit 2007. Archived (PDF) from the original on 15 February 2018.
- Richard Blish. "Dose Minimization During X-ray Inspection of Surface-Mounted Flash ICs" Archived 20 February 2016 at the Wayback Machine. p. 1.
- Richard Blish. "Impact of X-Ray Inspection on Spansion Flash Memory" Archived 4 March 2016 at the Wayback Machine.
- "SanDisk Extreme PRO SDHC/SDXC UHS-I Memory Card". Archived from the original on 27 January 2016. Retrieved 3 February 2016.
- "Samsung 32GB USB 3.0 Flash Drive FIT MUF-32BB/AM". Archived from the original on 3 February 2016. Retrieved 3 February 2016.
- Spansion. "What Types of ECC Should Be Used on Flash Memory?" Archived 4 March 2016 at the Wayback Machine. 2011.
- "DSstar: TOSHIBA ANNOUNCES 0.13 MICRON 1GB MONOLITHIC NAND". Tgc.com. 23 April 2002. Archived from the original on 27 December 2012. Retrieved 27 August 2013.
- Kim, Jesung; Kim, John Min; Noh, Sam H.; Min, Sang Lyul; Cho, Yookun (May 2002). "A Space-Efficient Flash Translation Layer for CompactFlash Systems" (PDF). Proceedings of the IEEE. 48 (2). pp. 366–375. Retrieved 15 August 2008.
- TN-29-07: Small-Block vs. Large-Block NAND flash Devices Archived 8 June 2013 at the Wayback Machine Explains 512+16 and 2048+64-byte blocks
- AN10860 LPC313x NAND flash data and bad block management Archived 3 March 2016 at the Wayback Machine Explains 4096+128-byte blocks.
- Thatcher, Jonathan (18 August 2009). "NAND Flash Solid State Storage Performance and Capability – an In-depth Look" (PDF). SNIA. Archived (PDF) from the original on 7 September 2012. Retrieved 28 August 2012.
- "Samsung ECC algorithm" (PDF). Samsung. June 2008. Archived (PDF) from the original on 12 October 2008. Retrieved 15 August 2008.
- "Open NAND Flash Interface Specification" (PDF). Open NAND Flash Interface. 28 December 2006. Archived (PDF) from the original on 27 July 2011. Retrieved 31 July 2010.
- A list of ONFi members is available at "Membership - ONFi". Archived from the original on 29 August 2009. Retrieved 21 September 2009..
- "Toshiba Introduces Double Data Rate Toggle Mode NAND In MLC And SLC Configurations". toshiba.com. Archived from the original on 25 December 2015.
- "Dell, Intel And Microsoft Join Forces To Increase Adoption Of NAND-Based Flash Memory In PC Platforms". REDMOND, Wash: Microsoft. 30 May 2007. Archived from the original on 12 August 2014. Retrieved 12 August 2014.
- See pages 5–7 of Toshiba's "NAND Applications Design Guide" under External links.
- NAND Flash 101: An Introduction to NAND Flash and How to Design It In to Your Next Product (PDF), Micron, pp. 2–3, TN-29-19, archived from the original (PDF) on 4 June 2016
- Pavan, Paolo; Bez, Roberto; Olivo, Piero; Zanoni, Enrico (1997). "Flash Memory Cells – An Overview" (PDF). Proceedings of the IEEE. 85 (8) (published August 1997). pp. 1248–1271. doi:10.1109/5.622505. Retrieved 15 August 2008.
- "The Fundamentals of Flash Memory Storage". 20 March 2012. Archived from the original on 4 January 2017. Retrieved 3 January 2017.
- "SLC NAND Flash Memory | TOSHIBA MEMORY | Europe(EMEA)".
- "Loading site please wait..." www.toshiba.com.
- "Serial Interface NAND | TOSHIBA MEMORY | Europe(EMEA)".
- "BENAND | TOSHIBA MEMORY | Europe(EMEA)".
- "SLC NAND Flash Memory | TOSHIBA MEMORY | Europe(EMEA)". business.toshiba-memory.com.
- "PBlaze4_Memblaze". memblaze.com. Retrieved 28 March 2019.
- Vättö, Kristian. "Testing Samsung 850 Pro Endurance & Measuring V-NAND Die Size". AnandTech. Archived from the original on 26 June 2017. Retrieved 11 June 2017.
- Vättö, Kristian. "Samsung SSD 845DC EVO/PRO Performance Preview & Exploring IOPS Consistency". AnandTech. p. 3. Archived from the original on 22 October 2016. Retrieved 11 June 2017.
- Vättö, Kristian. "Samsung SSD 850 EVO (120GB, 250GB, 500GB & 1TB) Review". AnandTech. p. 4. Archived from the original on 31 May 2017. Retrieved 11 June 2017.
- Vättö, Kristian. "Samsung SSD 845DC EVO/PRO Performance Preview & Exploring IOPS Consistency". AnandTech. p. 2. Archived from the original on 22 October 2016. Retrieved 11 June 2017.
- Ramseyer, Chris (9 June 2017). "Flash Industry Trends Could Lead Users Back to Spinning Disks". AnandTech. Retrieved 11 June 2017.
- "PBlaze5 700". memblaze.com. Retrieved 28 March 2019.
- "PBlaze5 900". memblaze.com. Retrieved 28 March 2019.
- "PBlaze5 910/916 series NVMe SSD". memblaze.com. Retrieved 26 March 2019.
- "PBlaze5 510/516 series NVMe™ SSD". memblaze.com. Retrieved 26 March 2019.
- "QLC NAND - What can we expect from the technology?". 7 November 2018.
- "Say Hello: Meet the World's First QLC SSD, the Micron 5210 ION". www.micron.com.
- "QLC NAND". www.micron.com.
- Tallis, Billy. "The Intel SSD 660p SSD Review: QLC NAND Arrives For Consumer SSDs". www.anandtech.com.
- "SSD endurance myths and legends articles on StorageSearch.com". www.storagesearch.com.
- "Samsung Announces QLC SSDs And Second-Gen Z-NAND". Tom's Hardware. 18 October 2018.
- "Samsung 860 QVO review: the first QLC SATA SSD, but it can't topple TLC yet". PCGamesN.
- "Samsung Electronics Starts Mass Production of Industry's First 4-bit Consumer SSD". news.samsung.com.
- "NAND Evolution and its Effects on Solid State Drive Useable Life" (PDF). Western Digital. 2009. Archived from the original (PDF) on 12 November 2011. Retrieved 22 April 2012.
- "A survey of address translation technologies for flash memories", ACM Computing Surveys, 2014.
- "Flash vs DRAM follow-up: chip stacking". The Daily Circuit. 22 April 2012. Archived from the original on 24 November 2012. Retrieved 22 April 2012.
- "Computer data storage unit conversion - non-SI quantity". Archived from the original on 8 May 2015. Retrieved 20 May 2015.
- Shilov, Anton (12 September 2005). "Samsung Unveils 2GB Flash Memory Chip". X-bit labs. Archived from the original on 24 December 2008. Retrieved 30 November 2008.
- Gruener, Wolfgang (11 September 2006). "Samsung announces 40 nm Flash, predicts 20 nm devices". TG Daily. Archived from the original on 23 March 2008. Retrieved 30 November 2008.
- "SanDisk Media Center". sandisk.com. Archived from the original on 19 December 2008.
- "SanDisk Media Center". sandisk.com. Archived from the original on 19 December 2008.
- https://www.pcworld.com/article/225370/look_out_for_the_256gb_thumb_drive_and_the_128gb_tablet.html; "Kingston outs the first 256GB flash drive". Archived from the original on 8 July 2017. Retrieved 28 August 2017. 20 July 2009, Kingston DataTraveler 300 is 256 GB.
- Borghino, Dario (31 March 2015). "3D flash technology moves forward with 10 TB SSDs and the first 48-layer memory cells". Gizmag. Archived from the original on 18 May 2015. Retrieved 31 March 2015.
- "Samsung Launches Monster 4TB 850 EVO SSD Priced at $1,499 | Custom PC Review". Custom PC Review. 13 July 2016. Archived from the original on 9 October 2016. Retrieved 8 October 2016.
- "Samsung Unveils 32TB SSD Leveraging 4th Gen 64-Layer 3D V-NAND | Custom PC Review". Custom PC Review. 11 August 2016. Archived from the original on 9 October 2016. Retrieved 8 October 2016.
- Master, Neal; Andrews, Mathew; Hick, Jason; Canon, Shane; Wright, Nicholas (2010). "Performance analysis of commodity and enterprise class flash devices" (PDF). IEEE Petascale Data Storage Workshop. Archived (PDF) from the original on 6 May 2016.
- "DailyTech - Samsung Confirms 32nm Flash Problems, Working on New SSD Controller". dailytech.com. Archived from the original on 4 March 2016.
- Clive Maxfield. "Bebop to the Boolean Boogie: An Unconventional Guide to Electronics". p. 232.
- Many serial flash devices implement a bulk read mode and incorporate an internal address counter, so that it is trivial to configure them to transfer their entire contents to RAM on power-up. When clocked at 50 MHz, for example, a serial flash could transfer a 64 Mbit firmware image in less than two seconds.
- Lyth0s (17 March 2011). "SSD vs. HDD". elitepcbuilding.com. Archived from the original on 20 August 2011. Retrieved 11 July 2011.
- "Flash Solid State Disks – Inferior Technology or Closet Superstar?". STORAGEsearch. Archived from the original on 24 December 2008. Retrieved 30 November 2008.
- Vadim Tkachenko (12 September 2012). "Intel SSD 910 vs HDD RAID in tpcc-mysql benchmark". MySQL Performance Blog.
- Matsunobu, Yoshinori. "SSD Deployment Strategies for MySQL." Archived 3 March 2016 at the Wayback Machine Sun Microsystems, 15 April 2010.
- "Samsung Electronics Launches the World's First PCs with NAND Flash-based Solid State Disk". Press Release. Samsung. 24 May 2006. Archived from the original on 20 December 2008. Retrieved 30 November 2008.
- "Samsung's SSD Notebook".
- "文庫本サイズのVAIO「type U」 フラッシュメモリー搭載モデル発売". www.sony.jp.
- "Sony Vaio UX UMPC – now with 32 GB Flash memory | NBnews.info. Laptop and notebook news, reviews, test, specs, price | Каталог ноутбуков, ультрабуков и планшетов, новости, обзоры".
- Douglas Perry (2012) Princeton: Replacing RAM with Flash Can Save Massive Power.
- "8-Bit AVR Microcontroller ATmega32A Datasheet Complete" (PDF). 19 February 2016. p. 18. Archived from the original (PDF) on 9 April 2016. Retrieved 29 May 2016.
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C
- "Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery" (PDF). 27 January 2015. p. 10. Archived (PDF) from the original on 7 October 2016. Retrieved 27 April 2016.
- "JEDEC SSD Specifications Explained" (PDF). p. 27.
- Yinug, Christopher Falan (July 2007). "The Rise of the Flash Memory Market: Its Impact on Firm Behavior and Global Semiconductor Trade Patterns" (PDF). Journal of International Commerce and Economics. Archived from the original (PDF) on 29 May 2008. Retrieved 19 April 2008.
- NAND memory market rockets Archived 8 February 2016 at the Wayback Machine, April 17, 2013, Nermin Hajdarbegovic, TG Daily, retrieved at 18 April 2013
- "Technology Roadmap for NAND Flash Memory". techinsights. April 2013. Archived from the original on 9 January 2015. Retrieved 9 January 2015.
- "Technology Roadmap for NAND Flash Memory". techinsights. April 2014. Archived from the original on 9 January 2015. Retrieved 9 January 2015.
- "NAND Flash Memory Roadmap" (PDF). TechInsights. June 2016.
- "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Retrieved 21 June 2019.
- Toshiba launches 24nm process NAND flash memory
- Lal Shimpi, Anand (2 December 2010). "Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates". Anandtech. Archived from the original on 3 December 2010. Retrieved 2 December 2010.
- Kim, Kinam; Koh, Gwan-Hyeob (16 May 2004). 2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716). 1. Serbia and Montenegro: Proceedings of the 24th International Conference on Microelectronics. pp. 377–384. doi:10.1109/ICMEL.2004.1314646. ISBN 978-0-7803-8166-7.
- "NAND Flash manufacturers' market share 2019". Statista. Retrieved 3 July 2019.
- "Toshiba: Inventor of Flash Memory". Toshiba. Retrieved 20 June 2019.
- "A chronological list of Intel products. The products are sorted by date" (PDF). Intel museum. Intel Corporation. July 2005. Archived from the original (PDF) on 9 August 2007. Retrieved 31 July 2007.
- "DD28F032SA Datasheet". Intel. Retrieved 27 June 2019.
- "Japanese Company Profiles" (PDF). Smithsonian Institution. 1996. Retrieved 27 June 2019.
- "Toshiba to Introduce Flash Memory Cards". Toshiba. 2 March 1995. Retrieved 20 June 2019.
- Cite error: The named reference
smithsonianwas invoked but never defined (see the help page).
- "WORLDWIDE IC MANUFACTURERS" (PDF). Smithsonian Institution. 1997. Retrieved 10 July 2019.
- "TOSHIBA ANNOUNCES 0.13 MICRON 1Gb MONOLITHIC NAND FEATURING LARGE BLOCK SIZE FOR IMPROVED WRITE/ERASE SPEED PERFORMANCE". Toshiba. 9 September 2002. Retrieved 11 March 2006.
- "TOSHIBA AND SANDISK INTRODUCE A ONE GIGABIT NAND FLASH MEMORY CHIP, DOUBLING CAPACITY OF FUTURE FLASH PRODUCTS". Toshiba. 12 November 2001. Retrieved 20 June 2019.
- "Our Proud Heritage from 2000 to 2009". Samsung Semiconductor. Samsung. Retrieved 25 June 2019.
- "TOSHIBA ANNOUNCES 1 GIGABYTE COMPACTFLASH™CARD". Toshiba. 9 September 2002. Retrieved 11 March 2006.
- "History: 2010s". SK Hynix. Retrieved 8 July 2019.
- "Samsung e·MMC Product family" (PDF). Samsung Electronics. December 2011. Retrieved 15 July 2019.
- "Toshiba Develops World's First 4-bit Per Cell QLC NAND Flash Memory". TechPowerUp. 28 June 2017. Retrieved 20 June 2019.
- Shilov, Anton (6 August 2018). "Samsung Starts Mass Production of QLC V-NAND-Based SSDs". AnandTech. Retrieved 23 June 2019.
- "Toshiba's flash chips could boost SSD capacity by 500 percent". Engadget. 20 July 2018. Retrieved 23 June 2019.
- McGrath, Dylan (20 February 2019). "Toshiba Claims Highest-Capacity NAND". EE Times. Retrieved 23 June 2019.
- Shilov, Anton (26 June 2019). "SK Hynix Starts Production of 128-Layer 4D NAND, 176-Layer Being Developed". AnandTech. Retrieved 8 July 2019.
- "Samsung Breaks Terabyte Threshold for Smartphone Storage with Industry's First 1TB Embedded Universal Flash Storage". Samsung. 30 January 2019. Retrieved 13 July 2019.
- Semiconductor Characterization System has diverse functions
- NAND Flash Applications Design Guide by Toshiba, April 2003 v. 1.0
- Understanding and selecting higher performance NAND architectures
- How flash storage works presentation by David Woodhouse from Intel
- Flash endurance testing
- COEN 180
- NAND Flash Data Recovery Cookbook
- Type of Flash Memory by OpenWrt