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'''Process–architecture–optimization''' is a development model for [[central processing unit]]s (CPUs) that [[Intel]] adopted in 2016. Under this three-phase (three-year) model, every [[microprocessor]] [[die shrink]] is followed by a [[microarchitecture]] change and then by an optimization. It replaced the two-phase (two-year) [[tick–tock model]] that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.<ref name="AnandTech 10nm delay">[https://www.anandtech.com/show/9447/intel-10nm-and-kaby-lake Tick Tock On The Rocks: Intel Delays 10nm, Adds 3rd Gen 14nm Core Product "Kaby Lake"]. AnandTech. 16 July 2015.</ref><ref>{{cite web|url=https://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization|title=Intel’s ‘Tick-Tock’ Seemingly Dead, Becomes ‘Process-Architecture-Optimization’|first=Ian|last=Cutress|publisher=}}</ref><ref name="ETEKNIX PAO">{{cite web|url=https://www.eteknix.com/intel-ditches-tick-tock-for-process-architecture-optimization/|title=Intel Ditches 'Tick-Tock' for 'Process-Architecture-Optimization' - eTeknix|first=|last=eTeknix.com|date=23 March 2016|publisher=}}</ref><ref>{{cite web|url=http://www.legitreviews.com/intel-tick-tock-processor-model-replaced-process-architecture-optimization_180140|title=Intel Tick-Tock Processor Model Replaced With Process-Architecture-Optimization - Legit Reviews|date=23 March 2016|publisher=}}</ref><ref>{{cite web|url=http://www.tomshardware.com/reviews/intel-7th-gen-core-kaby-lake-preview,4728-6.html|title=Intel 7th Gen Core: Process Architecture Optimization|date=30 August 2016|publisher=}}</ref>
'''Process–architecture–optimization''' is a development model for [[central processing unit]]s (CPUs) that [[Intel]] adopted in 2016. Under this three-phase (three-year) model, every [[microprocessor]] [[die shrink]] is followed by a [[microarchitecture]] change and then by one or more optimizations. It replaced the two-phase (two-year) [[tick–tock model]] that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.<ref name="AnandTech 10nm delay">[https://www.anandtech.com/show/9447/intel-10nm-and-kaby-lake Tick Tock On The Rocks: Intel Delays 10nm, Adds 3rd Gen 14nm Core Product "Kaby Lake"]. AnandTech. 16 July 2015.</ref><ref>{{cite web|url=https://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization|title=Intel’s ‘Tick-Tock’ Seemingly Dead, Becomes ‘Process-Architecture-Optimization’|first=Ian|last=Cutress|publisher=}}</ref><ref name="ETEKNIX PAO">{{cite web|url=https://www.eteknix.com/intel-ditches-tick-tock-for-process-architecture-optimization/|title=Intel Ditches 'Tick-Tock' for 'Process-Architecture-Optimization' - eTeknix|first=|last=eTeknix.com|date=23 March 2016|publisher=}}</ref><ref>{{cite web|url=http://www.legitreviews.com/intel-tick-tock-processor-model-replaced-process-architecture-optimization_180140|title=Intel Tick-Tock Processor Model Replaced With Process-Architecture-Optimization - Legit Reviews|date=23 March 2016|publisher=}}</ref><ref>{{cite web|url=http://www.tomshardware.com/reviews/intel-7th-gen-core-kaby-lake-preview,4728-6.html|title=Intel 7th Gen Core: Process Architecture Optimization|date=30 August 2016|publisher=}}</ref>


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Revision as of 17:41, 2 February 2021

Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.[1][2][3][4][5]

Wave[6] Process
(shrink)
Architecture Optimizations
1:
14 nm
2014:
Broadwell
(5th gen)
2015:
Skylake
(6th gen)
2016:
Kaby Lake
(7th gen)
2017:
Coffee Lake
(8th gen)
2018:
Coffee Lake Refresh
(9th gen)
2019:

Comet Lake

(10th gen)

References: [1][3][6][7]
2:
10 nm
2018:[note 1]
Cannon Lake
(8th gen, Palm Cove)
2019:
Ice Lake
(10th gen, Sunny Cove)
2020:
Tiger Lake
(11th gen, Willow Cove)
2021:
Alder Lake
(12th gen, Golden Cove)
References: [1][8][7]
3:
7 nm
2022:
Meteor Lake
(13th gen, Redwood Cove)
References:

Notes

  1. ^ Cannon Lake: only 1 CPU released, microarchitecture dumped 1.5 year later.

References

  1. ^ a b c Tick Tock On The Rocks: Intel Delays 10nm, Adds 3rd Gen 14nm Core Product "Kaby Lake". AnandTech. 16 July 2015.
  2. ^ Cutress, Ian. "Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'".
  3. ^ a b eTeknix.com (23 March 2016). "Intel Ditches 'Tick-Tock' for 'Process-Architecture-Optimization' - eTeknix".
  4. ^ "Intel Tick-Tock Processor Model Replaced With Process-Architecture-Optimization - Legit Reviews". 23 March 2016.
  5. ^ "Intel 7th Gen Core: Process Architecture Optimization". 30 August 2016.
  6. ^ a b Intel Launches 7th Generation Kaby Lake: 15W/28W with Iris, 35-91W Desktop and Mobile Xeon - 03 January 2017. "Kaby Lake is the first wave of Intel’s ‘Optimization’ step in their ‘Process, Architecture, Optimization’ release structure."
  7. ^ a b Intel’s Path to 10nm: 2010 to 2019 - 25 January 2019
  8. ^ Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review - 25 January 2019.